SSD1905QT2(2002) 데이터 시트보기 (PDF) - Solomon Systech

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SSD1905QT2
(Rev.:2002)

LCD Graphics Controller

Solomon Systech  

5.3 Clock Input

Pin Name Type

CLKI

I

AUXCLK

I

Table 5-3 : Clock Input Pin Descriptions

TQFP

Pin #

15

77

Cell

RESET#

State

Description

LIS

—

Typically used as input clock source for bus clock and

memory clock

This pin may be used as input clock source for pixel

LIS

—

clock. This input pin must be connected to VSS if not

used.

5.4 Miscellaneous

Pin Name Type

CF[7:0]

I

GPO

O

TESTEN

I

Table 5-4 : Miscellaneous Pin Descriptions

TQFP

Pin #

Cell

RESET

# State

Description

These inputs are used to configure the SSD1905 – see

Table 5-6 : Summary of Power-On/Reset Options.

78-85 LIS

47

LO3

86

LIS

—

Note: These pins are used for configuration of the

SSD1905 and must be connected directly to IOVDD

or VSS .

0

General Purpose Output (possibly used for controlling

the LCD power).

—

Test Enable input used for production test only and

should be tied to VSS.

5.5 Power and Ground

Pin Name

IOVDD

COREVDD

VSS

Type

P

P

P

Table 5-5 : Power And Ground Pin Descriptions

TQFP

Pin #

16, 26,

37, 49,

63, 76

1, 51

14, 25,

36, 50,

62, 75,

100

Cell

RESET

# State

Description

P

—

Power supply pins. It is recommended to place a

0.1µF bypass capacitor close to each of these pins.

COREVDD pins are internal voltage regulator output

pins that is used by the internal circuitry only. They

P

—

cannot be used for driving external circuitry.

It is required to place a 0.1µF bypass capacitor

close to each of these pins.

P

—

Ground pins

5.6 Summary of Configuration Options

These pins are used for configuration of the SSD1905 and must be connected directly to IOVDD or VSS. The state

of CF[5:0] is latched on the rising edge of RESET# or after the software reset function is activated (REG[A2h] bit

0). Changing state at any other time has no effect.

SOLOMON

Rev 1.3

10/2002

10

SSD1905

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