MC33385DH/R2 데이터 시트보기 (PDF) - Freescale Semiconductor

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MC33385DH/R2

Quad Low-side Driver

Freescale Semiconductor 

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The device is a Quad Low-side Driver driven by four

CMOS input stages. Each output power transistor is

protected against short to VBAT by a zener clamp against

overvoltage.

A diagnostic logic recognizes four failure types at the

output stage : overcurrent, short to GND, open-load and

overtemperature.

The failures are individually stored in a byte which can be

read out via the serial interface (SPI).

OUTPUT STAGE CONTROL

Each of the four output stages is switched ON and OFF by

an individual control line (NON-Input). The logic level of the

control line is CMOS compatible. The output transistors are

switched off when the inputs are not connected.

POWER TRANSISTORS

Each of the four output stages has its own zener clamp.

This causes a voltage limitation at the power transistors when

inductive loads are switched off. The drain voltage ramp

occurring when output is switched on or off, is within defined

limits. Output transistors can be connected in parallel to

increase current capability. In this case, the associated inputs

should be connected together.

SHORT-CIRCUIT AND OVERTEMPERATURE

PROTECTION

If the output current increases above the short current limit

for a time longer than tSCB or if the temperature increases

above TOFF then the power transistor is immediately

switched off. It remains switched off until the control signal on

the NON-Input is switched off and on again.

DIAGNOSTICS

The following failures at the output stage are recognized :

Short -Circuit to VBAT or overtemp = SCB (Highest priority)

Short -Circuit to GND.................... = SCG

Open Load...................................... = OL (Lowest priority)

The SCB failure is recognized by an overcurrent (current

above the short current limit) or an overtemperature.

If the current through the output stage is lower than the

IOL-reference, after a filter time an OL failure will be

recognized. This measurement is active while the power

stage is switched on.

The SCG failure will recognize when the drain voltage is

lower than the OL reference limit, while the output stage is

switched off. All four outputs have an independent

overtemperature detection and shutdown. All failures are

stored in individual registers.

They can be read by the microprocessor via the serial

interface. There is no failure detected if the power stage

control time is shorter than the filter time.

DIAGNOSTIC INTERFACE

The communication between the microprocessor and the

failure register runs via the SPI link. If there is a failure stored

in the failure register, the first bit of the shift register is set to

a high level. With the High/Low change on the NCS pin, the

first bit of the diagnostic shift register will be transmitted to the

SDO output. The SDO output is the serial output from the

diagnostic shift register and it is put into a tri-state when the

NCS pin is high. The CLK pin clocks the diagnostic shift

register. New SDO data will appear on every rising edge of

this pin and new SDI data will be latched on every CLK’s

falling edge into the shift register. With the first positive pulse

of the CLK, the failure register will be cleared. There is no bus

collision at a small spike at the NCS. The CLK is always LOW

while the NCS-signal is changing.

RESET

There are two different reset functions realized :

Under voltage reset : as long as the VCC voltage is lower

than VCCRES, the power stages are switched off and the

failure-registers are reset.

Reset pin : as long as the NRES-pin is low, following

circuits are reset :

• Power stages

• Failure register

UNDERVOLTAGE PROTECTION

At low VCC voltage, the device remains switched off even

if there is a voltage ramp at the OUT pin.

33385

14

Analog Integrated Circuit Device Data

Freescale Semiconductor

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