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MC33975TEKR2

Multiple Switch Detection Interface with Suppressed Wake-up and 32 mA Wetting Current

Freescale Semiconductor 

FUNCTIONAL DESCRIPTIONS

INTRODUCTION

FUNCTIONAL DESCRIPTIONS

INTRODUCTION

The 33975 device is an integrated circuit designed to provide

systems with ultra-low quiescent sleep/wake-up modes and

a robust interface between switch contacts and a

microprocessor. The 33975 replaces many of the discrete

components required when interfacing to microprocessor-

based systems while providing switch ground offset

protection, contact wetting current, and system wake-up.

The 33975 features 8-programmable switch-to-ground or

switch-to-battery inputs and 14 switch-to-ground inputs. All

switch inputs may be read as analog inputs through the

analog multiplexer (AMUX). Other features include a

programmable wake-up timer, programmable interrupt timer,

programmable wake-up/interrupt bits, and programmable

wetting current settings.

This device is designed primarily for automotive applications

but may be used in a variety of other applications such as

computer, telecommunications, and industrial controls.

FUNCTIONAL PIN DESCRIPTION

CHIP SELECT (CS)

The system MCU selects the 33975 to receive

communication using the chip select (CS) pin. With CS in a

logic low state, command words may be sent to the 33975 via

the serial input (SI) pin, and switch status information can be

received by the MCU via the serial output (SO) pin. The

falling edge of CS enables the SO output, latches the state of

the INT pin, and the state of the external switch inputs.

Rising edge of the CS initiates the following sequence:

1. Disables the SO driver (high-impedance)

2. INT pin is reset to logic [1], except when additional

switch changes occur during CS low (see Figure 6,

page 11).

3. Activates the received command word, allowing the

33975 to act upon new data from switch inputs.

To avoid any spurious data, it is essential the high-to-low and

low-to-high transitions of the CS signal occur only when

SCLK is in a logic low state. A clean CS signal is needed to

ensure no incomplete SPI words are sent to the device.

Internal to the 33975 device is an active pull-up to VDD on CS.

In Sleep Mode the negative edge of CS (VDD applied) will

wake up the 33975 device. Data received from the device

during CS wake-up may not be accurate.

SERIAL CLOCK (SCLK)

The system clock (SCLK) pin clocks the internal shift register

of the 33975. The SI data is latched into the input shift

register on the falling edge of SCLK signal. The SO pin shifts

the switch status bits out on the rising edge of SCLK. The SO

data is available for the MCU to read on the falling edge of

SCLK. False clocking of the shift register must be avoided to

ensure validity of data. It is essential the SCLK pin be in a

logic low state whenever CS makes any transition. For this

reason, it is recommended, though not necessary, that the

SCLK pin is commanded to a low logic state as long as the

device is not accessed and CS is in a logic high state. When

the CS is in a logic high state, any signal on the SCLK and SI

pin will be ignored and the SO pin is tri-state.

SERIAL INPUT (SI)

The SI pin is used for serial instruction data input. SI

information is latched into the input register on the falling

edge of SCLK. A logic high state present on SI will program

a one in the command word on the rising edge of the CS

signal. To program a complete word, 24 bits of information

must be entered into the device.

SERIAL OUTPUT (SO)

The SO pin is the output from the shift register. The SO pin

remains tri-stated until the CS pin transitions to a logic low

state. All open switches are reported as a zero, all closed

switches are reported as a one. The negative transition of CS

enables the SO driver.

The first positive transition of SCLK will make the status data

bit 24 available on the SO pin. Each successive positive clock

will make the next status data bit available for the MCU to

read on the falling edge of SCLK. The SI/SO shifting of the

data follows a first-in-first-out protocol, with both input and

output words transferring the most significant bit (MSB) first.

INTERRUPT OUTPUT (INT)

The INT pin is an interrupt output from the 33975 device. The

INT pin is an open-drain output with an internal pull-up to

VDD. In Normal mode, a switch state change will trigger the

INT pin (when enabled). The INT pin is latched on the falling

edge of CS, and cleared on the rising edge of CS. The INT pin

will not clear with rising edge of CS if a switch contact change

has occurred while the CS was low.

In a multiple 33975 device system with WAKE high and VDD

in (Sleep mode), the falling edge of INT will place all 33975s

in Normal mode.

WAKE INPUT (WAKE)

The WAKE pin is an open-drain output and a wake-up input.

The pin is designed to control a power supply Enable pin. In

the Normal mode, the WAKE pin is low. In the Sleep mode,

the WAKE pin is high. The WAKE pin has a pull-up to the

internal +5.0 V supply.

33975

12

Analog Integrated Circuit Device Data

Freescale Semiconductor

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