HS1B-2700RH-Q 데이터 시트보기 (PDF) - Intersil
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HS1B-2700RH-Q Datasheet PDF : 6 Pages
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HS-2700RH
Test Circuit
400
10K
1 OPEN
2 S3A
S1 1
OPEN 2
S2 1
OPEN 2
10K 2 S3B
100
1
OPEN
VAC
100
50K
NOTE: Includes stray capacitances.
Timing Waveforms
1.6K
0.1 1
+VCC
ACOUT
75pF (NOTE)
2
1 S5A
1 S6
-
DUT
+
2
0.1 1
2
S5B 1
OPEN 1
500K
OPEN S9
S8
12
2
V2
2K
-VEE
-1/10
V1
FOR LOOP STABILITY,
USE MIN VALUE CAPACITOR
TO PREVENT OSCILLATION
50K
- -1
+
-
+
BUFFER
x2
EOUT
ALL RESISTORS = ±1% (Ω)
ALL CAPACITORS = ±10% (µF)
VIN
+
-
VOUT
1.6K
75pF
400
FIGURE 1. SIMPLIFIED TEST CIRCUIT
+1.0V
INPUT
-1.0V
+4V
OUTPUT
-4V
+2.5V
-2.5V
∆T
∆V
SLEW
RATE
= ∆V/∆T
+40mV
INPUT
0V
OVERSHOOT
+160mV
90%
OUTPUT
10%
0V
RISE TIME
0V
-40mV
FIGURE 2. SLEW RATE WAVEFORM
FIGURE 3. TRANSIENT RESPONSE WAVEFORM
NOTE: Measured on both positive and negative transitions. Capacitance at Compensation pin should be minimized.
2
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