74VHC112(2007) 데이터 시트보기 (PDF) - Fairchild Semiconductor

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74VHC112
(Rev.:2007)

Dual J-K Flip-Flops with Preset and Clear

Fairchild Semiconductor 

Connection Diagram

Pin Description

Pin Names

J1, J2, K1, K2

CLK1, CLK2

CLR1, CLR2

PR1, PR2

Q1, Q2, Q1, Q2

Description

Data Inputs

Clock Pulse Inputs (Active Falling

Edge)

Direct Clear Inputs (Active LOW)

Direct Preset Inputs (Active LOW)

Outputs

Truth Table

Inputs

Outputs

PR CLR CP J K Q

Q

L

H

X

XX

H

L

H

L

X

XX

L

H

L

L

X

XX

H

H

H

H

H

H

h

h

Q0

Q0

l

h

L

H

H

H

h

l

H

L

H

H

l

l

Q0

Q0

H (h) = HIGH Voltage Level

L (l) = LOW Voltage Level

X = Immaterial

= HIGH-to-LOW Clock Transition

Q0 (Q0) = Before HIGH-to-LOW Transition of Clock

Lower case letters indicate the state of the referenced

input or output one setup time prior to the HIGH-to-LOW

clock transition.

Logic Diagram

(One Half Shown)

©1995 Fairchild Semiconductor Corporation

74VHC112 Rev. 1.2

2

www.fairchildsemi.com

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