ADJD-J823 데이터 시트보기 (PDF) - Avago Technologies
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ADJD-J823 Datasheet PDF : 18 Pages
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To read from a register, the master first generates a START condition. Then it sends the slave address for the device it
wants to communicate with. The least significant bit (LSB) of the slave address must indicate that the master wants
to write to the slave. The addressed device will then acknowledge the master.
The master writes the register address it wants to access and waits for the slave to acknowledge. The master then
generates a repeated START condition and resends the slave address sent previously. The least significant bit (LSB)
of the slave address must indicate that the master wants to read from the slave. The addressed device will then ac-
knowledge the master.
The master reads the register data sent by the slave and sends a no acknowledge signal to stop reading. The master
then generates a STOP condition to end the data transfer.
Start condition
Master will write data
Repeated start
condition
Master will read data
Stop condition
S A6 A5 A4 A3 A2 A1 A0 W A D7 D6 D5 D4 D3 D2 D1 D0 A Sr A6 A5 A4 A3 A2 A1 A0 R A D7 D6 D5 D4 D3 D2 D1 D0 A P
Master sends
slave address
Master writes
register address
Master sends
slave address
Master reads
register data
Slave acknowledge
Slave acknowledge
Slave acknowledge
Master not
acknowledge
Figure 10. Register Byte Read Protocol
Application Diagrams
HOST
SYSTEM
XRST
SLEEP
SDA
SCL
Connect pull-up
resistor to SDA
10 XRST
15 SLEEP
12 SDASLV
11 SCLSLV
NC
CLKIO
1, 20
9
PWMR 4
PWMG 3
PWMB 2
Float
Float
RGB LED DRIVER
ENABLE_RED
ENABLE_GREEN
ENABLE_BLUE
SDAPROM
14
SCLPROM
13
I2C SERIAL
EEPROM
SDA
SCL
Connect pull-up
resistor to SDA
AVDD
19
Voltage
Regulator
AGND
8, 16,
17, 18
DGND
5, 6
DVDD
7
Voltage
Regulator
Star-connected ground
15
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