CY7C68001(2004) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C68001 Datasheet PDF : 42 Pages
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FO R
FO R
CY7C68001
Full Speed Non-ISO Mode:
EP2PFH, EP6PFH
0x12, 0x16
Bit #
7
6
5
4
3
21
0
Bit Name
DECIS PKTSTAT OUT: OUT: OUT: 0 PFC9 IN:
PFC12 PFC11 PFC10
PKTS[2]
OUT:
PFC8
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default
1
0
0
0
1
00
0
Full Speed Non-ISO Mode:
EP4PFH, EP8PFH
Bit #
7
6
Bit Name DECIS PKT-
STAT
Read/Write R/W R/W
Default
0
0
0x14, 0x18
5
4
3
21
0
0 OUT: OUT: 0
PFC10 PFC9
0 PFC8
R/W R/W R/W R/W R/W R/W
0
0
1
00
0
7.7.1 DECIS: EPxPFH.7
If DECIS = 0, then PF goes high when the byte count i is equal
to or less than what is defined in the PF registers. If DECIS =
1 (default), then PF goes high when the byte count equal to or
greater than what is set in the PF register. For OUT endpoints,
the byte count is the total number of bytes in the FIFO that are
available to the external master. For IN endpoints, the byte
count is determined by the PKSTAT bit.
7.7.2 PKSTAT: EPxPFH.6
For IN endpoints, the PF can apply to either the entire FIFO,
comprising multiple packets, or only to the current packet
being filled. If PKTSTAT = 0 (default), the PF refers to the entire
IN endpoint FIFO. If PKTSTAT = 1, the PF refers to the number
of bytes in the current packet.
PKTSTAT
PF applies to
0 Number of committed
packets + current packet
bytes
1 Current packet bytes only
EPnPFH:L
format
PKTS[] and PFC[]
PFC[ ]
7.7.3 IN: PKTS(2:0)/OUT: PFC[12:10]: EPxPFH[5:3]
These three bits have a different meaning, depending on
whether this is an IN or OUT endpoint.
7.7.3.1 IN Endpoints
If IN endpoint, the meaning of this EPxPFH[5:3] bits depend
on the PKTSTAT bit setting. When PKTSTAT = 0 (default), the
PF considers when there are PKTS packets plus PFC bytes in
the FIFO. PKTS[2:0] determines how many packets are
considered, according to the following table.
Table 7-5. PKTS Bits
PKTS2
0
0
0
0
PKTS1
0
0
1
1
PKTS0
0
1
0
1
Number of Packets
0
1
2
3
Table 7-5. PKTS Bits (continued)
PKTS2
1
PKTS1
0
PKTS0
0
Number of Packets
4
When PKTSTAT = 1, the PF considers when there are PFC
bytes in the FIFO, no matter how many packets are in the
FIFO. The PKTS[2:0] bits are ignored.
7.7.3.2 OUT Endpoints
The PF considers when there are PFC bytes in the FIFO
regardless of the PKTSTAT bit setting.
7.8 EPxISOINPKTS Registers 0x1A–0x1D
EP2ISOINOKTS, EP4ISOINPKTS,
EP6ISOINPKTS, EP8ISOINPKTS
Bit #
7
6
5
4
Bit Name
0
0
0
0
Read/Write R/W R/W R/W R/W
Default
0
0
0
0
0x1A, 0x1B,
0x1C, 0x1D
3
2
1
0
0 INPPF2 INPPF1 INPPF0
R/W R/W R/W R/W
0
0
0
1
For ISOCHRONOUS IN endpoints only, these registers
determine the number of packets per frame (only one per
frame for full-speed mode) or microframe (up to three per
microframe for high-speed mode), according to the following
table.
Table 7-6. EPxISOINPKTS
INPPF1
0
0
1
1
INPPF0
0
1
0
1
Packets
Invalid
1 (default)
2
3
7.9 EPxxFLAGS Registers 0x1E–0x1F
The EPxxFLAGS provide an alternate way of checking the
status of the endpoint FIFO flags. If enabled, the SX2 can
interrupt the external master when a flag is asserted, and the
external master can read these two registers to determine the
state of the FIFO flags. If the INFM1 and/or OEP1 bits are set,
then the EPxEF and EPxFF bits are actually empty +1 and full
–1.
EP24FLAGS
0x1E
Bit #
7
6
5
4
3
2
1
0
Bit Name
0 EP4PF EP4EF EP4FF 0 EP2PF EP4EF EP4FF
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default
0
0
1
0
0
0
1
0
EP68FLAGS
0x1F
Bit #
7
6
5
4
3
2
1
0
Bit Name
0 EP8PF EP8EF EP8FF 0 EP6PF EP6EF EP6FF
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default
0
0
1
0
0
0
1
0
7.9.1 EPxPF Bit 6, Bit 2
This bit is the current state of endpoint x’s programmable flag.
Document #: 38-08013 Rev. *E
Page 19 of 42
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