CY7C68001(2004) 데이터 시트보기 (PDF) - Cypress Semiconductor

부품명

상세내역

제조사

CY7C68001
(Rev.:2004)

High-Speed USB Interface Device

Cypress Semiconductor 

FO R

FO R

CY7C68001

FIFO is driven on the data bus (SLOE must also be asserted)

and then the FIFO pointer is incremented.

11.6.4 Sequence Diagram of a Single and Burst Asynchronous Write

tSFA

tFAH

tSFA

FIFOADR

t=0

tWRpwl tWRpwh

T=0

tWRpwl tWRpwh

tWRpwl tWRpwh

tWRpwl tWRpwh

SLWR

t =1

t=3

T=1

T=3

T=4

T=6

T=7

T=9

SLCS

FLAGS

DATA

PKTEND

tXFLG

tSFD tFDH

N

t=2

tSFD tFDH

N+1

T=2

tSFD tFDH

N+2

T=5

tSFD tFDH

N+3

T=8

tFAH

tXFLG

tPEpwl

tPEpwh

Figure 11-20. Slave FIFO Asynchronous Write Sequence and Timing Diagram[12]

Figure 11-20 diagrams the timing relationship of the SLAVE

FIFO write in an asynchronous mode. The diagram shows a

single write followed by a burst write of 3 bytes and committing

the 4-byte-short packet using PKTEND.

·At t = 0 the FIFO address is applied, insuring that it meets the

setup time of tSFA. If SLCS is used, it must also be asserted

(SLCS may be tied low in some applications).

· ..At t = 1 SLWR is asserted. SLWR must meet the minimum

active pulse of tWRpwl and minimum de-active pulse width of

tWRpwh. If the SLCS is used, it must be in asserted with SLWR

or before SLWR is asserted.

·At t = 2, data must be present on the bus tSFD before the de-

asserting edge of SLWR.

·At t = 3, de-asserting SLWR will cause the data to be written

from the data bus to the FIFO and then increments the FIFO

pointer. The FIFO flag is also updated after tXFLG from the de-

asserting edge of SLWR.

The same sequence of events are shown for a burst write and

is indicated by the timing marks of T = 0 through 5. Note: In

the burst write mode, once SLWR is de-asserted, the data is

written to the FIFO and then the FIFO pointer is incremented

to the next byte in the FIFO. The FIFO pointer is post incre-

mented.

In Figure 11-20 once the four bytes are written to the FIFO and

SLWR is deasserted, the short 4-byte packet can be

committed to the host using the PKTEND. The external device

should be designed to not assert SLWR and the PKTEND

signal at the same time. It should be designed to assert the

PKTEND after SLWR is deasserted and met the minimum de-

asserted pulse width. The FIFOADDR lines are to be held

constant during the PKTEND assertion.

Document #: 38-08013 Rev. *E

Page 34 of 42

Share Link: