GT28F160F3F3B150 데이터 시트보기 (PDF) - Intel
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GT28F160F3F3B150 Datasheet PDF : 47 Pages
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E
FAST BOOT BLOCK DATASHEET
3.1.5
RESET
The device enters a reset mode when RST# is
driven low. In reset mode, internal circuitry is turned
off and outputs are placed in a high-impedance
state.
If RP# is taken low during a block erase or program
operation, the operation will be aborted and the
memory contents at the aborted location are no
longer valid. See Figure 21 for detailed information
regarding reset timings.
After return from reset, a time tPHQV is required until
outputs are valid, and a delay (tPHWL or tPHEL) is
required before a write sequence can be initiated.
After this wake-up interval, normal operation is
restored. The device defaults to read array mode,
the status register is set to 80H, and the read
configuration register defaults to asynchronous
page-mode reads.
4.0 COMMAND DEFINITIONS
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.
Table 2. Bus Operations
Mode
Reset
Standby
Output Disable
Read
Read Identifier
Codes
Notes
1,2
RST#
VIL
VIH
VIH
VIH
VIH
CE#
X
VIH
VIL
VIL
VIL
ADV#
X
X
X
VIL
VIL
OE#
X
X
VIH
VIL
VIL
WE# Address VPP
X
X
X
X
X
X
VIH
X
X
VIH
X
X
VIH
See
X
Table 4
DQ0–15
High Z
High Z
High Z
DOUT
See
Table 4
Write
3,4
VIH
VIL
VIL
VIH
VIL
X
X
DIN
NOTES:
1. Refer to DC Characteristics. When VPP ≤ VPPLK, memory contents can be read, but not altered.
2. X can be VIL or VIH for control and address input pins and VPPLK or VPPH1/2 for VPP. See DC Characteristics for VPPLK and
VPPH1/2 voltages.
3. Command writes involving block erase or program are reliably executed when VPP = VPPH1/2 and VCC = VCC1/2
(see Section 8 for operating conditions at different temperatures).
4. Refer to Table 3 for valid DIN during a write operation.
PRODUCT PREVIEW
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