DE28F800B3B150 데이터 시트보기 (PDF) - Intel
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DE28F800B3B150 Datasheet PDF : 47 Pages
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FAST BOOT BLOCK DATASHEET
4.6 Program Command
Program operation is executed by a two-cycle
command sequence. Program setup (standard 40H
or alternate 10H) is written, followed by a second
write that specifies the address and data. The WSM
then takes over, controlling the internal program
algorithm. After the program sequence is written,
the device automatically outputs status register
data when read (see Figure 8, Automated Program
Flowchart). The CPU can detect the completion of
the program event by analyzing status register bit
SR.7.
When the program operation completes, check
status register bit SR.4 for an error flag (“1”). If an
error is detected, check status register bits SR.5,
SR.3, and SR.1 to understand what caused the
problem. After examining the status register, it
should be cleared if an error was detected before
issuing a new command. The device will remain in
status register read mode until another command is
written to the CUI.
4.7 Block Erase Suspend/Resume
Command
The Block Erase Suspend command allows block
erase interruption to read or program data in
another blocks. Once the block erase process
starts, writing the Block Erase Suspend command
requests that the WSM suspend the block erase
operation after a certain latency period. The device
continues to output status register data when read
after the Block Erase Suspend command is issued.
Status Register bits SR.7 and SR.6 indicate when
the block erase operation has been suspended
(both will be set to “1”). Specification tWHRH2 defines
the block erase suspend latency.
At this point, a Read Array command can be written
to read data from blocks other than that which is
suspended. A Program command sequence can
also be issued during erase suspend to program
data in other blocks. Using the Program Suspend
command (see Section 4.8), a program operation
can be suspended during an erase suspend. The
only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume.
During a block erase suspend, the chip can go into
a pseudo-standby mode by taking CE# to VIH,
which reduces active current draw. VPP must
remain at VPPH1/2 while block erase is suspended.
WP# must also remain at VIL or VIH.
To resume the block erase operation, write the
Block Erase Resume command to the CUI. This will
automatically clear status register bits SR.6 and
SR.7. After the Erase Resume command is written,
the device automatically outputs status register
data when read (see Figure 9, Block Erase
Suspend/Resume Flowchart). Block erase cannot
resume until program operations initiated during
block erase suspend have completed.
4.8 Program Suspend/Resume
Command
The Program Suspend command allows program
interruption to read data in other flash memory
locations. Once the program process starts, writing
the Program Suspend command requests that the
WSM suspend the program operation after a certain
latency period. The device continues to output
status register data when read after issuing
Program Suspend command. Status register bits
SR.7 and SR.2 indicate when the block erase
operation has been suspended (both will be set to
“1”). Specification tWHRH1 defines the program
suspend latency.
At this point, a Read Array command can be written
to read data from blocks other than that which is
suspended. The only other valid commands while
block erase is suspended are Read Status Register
and Program Resume.
During a program suspend, the chip can go into a
pseudo-standby mode by taking CE# to VIH, which
reduces active current draw. VPP must remain at
VPPH1/2 while program is suspended. WP# must
also remain at VIL or VIH.
To resume the program, write the Program Resume
command to the CUI. This will automatically clear
status register bits SR.7 and SR.2. After the Erase
Resume command is written, the device
automatically outputs status register data when
read (see Figure 10, Program Suspend/Resume
Flowchart).
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