DE28F800B3B150 데이터 시트보기 (PDF) - Intel
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DE28F800B3B150 Datasheet PDF : 47 Pages
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FAST BOOT BLOCK DATASHEET
E
Start
Write 20H,
Block Address
Write D0H,
Block Address
Read Status Register
0
SR.7 =
1
Full Status
Check if Desired
Suspend
Blk. Erase
Loop
No
Suspend
Block Erase Yes
Block Erase Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
1
SR.3 =
0
1
SR.1 =
VPP Range Error
Device Protect Error
0
SR.4, 5 =
0
SR.5 =
0
Block Erase
Successful
1
Command Sequence
Error
1
Block Erase Error
Bus Operation
Write
Write
Read
Command
Comments
Erase Setup
Erase Confirm
Data = 20H
Addr = Within Block to Be
Erased
Data = D0H
Addr = Within Block to Be
Erased
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent block erasures.
Full status check can be done after each block erase or after a
sequence of block erasures.
Write FFH after the last operation to place device in read array mode.
Bus Operation
Command
Comments
Standby
Standby
Standby
Standby
Check SR.3
1 = VPP Error Detect
Check SR.1
1 = Device Protect Detect
WP# = VIL
Check SR.4, 5
Both 1 = Command Sequence
Error
Check SR.5
1 = Block Erase Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Staus
Register command, in cases where multiple blocks are erased before
full status is checked.
If an error is detected, clear the status register before attempting retry
or other error recovery.
Figure 7. Automated Block Erase Flowchart
22
PRODUCT PREVIEW
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