DT28F800F3F3B120 데이터 시트보기 (PDF) - Intel
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DT28F800F3F3B120 Datasheet PDF : 47 Pages
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7.3 Standby Power
With CE# at a logic-high level (VIH) and the CUI in
read mode, the flash memory is in standby mode,
which disables much of the device’s circuitry and
substantially reduces power consumption. Outputs
(DQ0–DQ15) are placed in a high-impedance state
independent of the status of the OE# signal. If CE#
transitions to a logic-high level during erase or
program operations, the device will continue to
perform the operation and consume corresponding
active power until the operation is completed.
System engineers should analyze the breakdown of
standby time versus active time and quantify the
respective power consumption in each mode for
their specific application. This will provide a more
accurate measure of application-specific power and
energy requirements.
7.4 Power-Up/Down Operation
The device is protected against accidental block
erasure or programming during power transitions.
Power supply sequencing is not required, since the
device is indifferent as to which power supply, VPP,
VCC, or VCCQ, powers-up first.
7.4.1
RST# CONNECTION
The use of RST# during system reset is important
with automated program/erase devices since the
system expects to read from the flash memory
when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU
initialization will not occur because the flash
memory may be providing status information
instead of array data. Intel recommends connecting
RST# to the system reset signal to allow proper
CPU/flash initialization following system reset.
System designers must guard against spurious
writes when VCC voltages are above VLKO and VPP
is active. Since both WE# and CE# must be low for
a command write, driving either signal to VIH will
inhibit writes to the device. The CUI architecture
provides additional protection since alteration of
memory contents can only occur after successful
completion of the two-step command sequences.
The device is also disabled until RST# is brought to
VIH, regardless of the state of its control inputs. By
holding the device in reset during power-up/down,
invalid bus conditions during power-up can be
masked, providing yet another level of memory
protection.
PRODUCT PREVIEW
7.4.2
VCC, VPP AND RST# TRANSITIONS
The CUI latches commands as issued by system
software and is not altered by VPP or CE#
transitions or WSM actions. Its default state upon
power-up, after exit from deep power-down mode or
after VCC transitions above VLKO (Lockout voltage),
is read array mode.
After any block erase or program operation is
complete (even after VPP transitions down to
VPPLK), the CUI must be reset to read array mode
via the Read Array command if access to the flash
memory array is desired.
7.5 Power Supply Decoupling
Flash memory’s power switching characteristics
require careful device decoupling. System
designers should consider three supply current
issues:
1. Standby current levels (ICCS)
2. Active current levels (ICCR)
3. Transient peaks produced by falling and rising
edges of CE#.
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 µF ceramic
capacitor connected between each VCC and GND,
and between its VPP and GND. These high-
frequency, inherently low-inductance capacitors
should be placed as close as possible to the
package leads.
7.5.1
VPP TRACE ON PRINTED CIRCUIT
BOARDS
Designing for in-system writes to the flash memory
requires special consideration of the VPP power
supply trace by the printed circuit board designer.
The VPP pin supplies the flash memory cells current
for programming and erasing. VPP trace widths and
layout should be similar to that of VCC. Adequate
VPP supply traces, and decoupling capacitors
placed adjacent to the component, will decrease
spikes and overshoots.
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