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PM5350-RC 데이터 시트보기 (PDF) - PMC-Sierra

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PM5350-RC Datasheet PDF : 196 Pages
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DATA SHEET
PMC-960924
ISSUE 5
PM5350 S/UNI-ULTRA
SATURN USER NETWORK INTERFACE
performs framing (A1, A2), descrambling, detects alarm conditions, and monitors
section, line, and path bit interleaved parity (B1, B2, B3), accumulating error
counts at each level for performance monitoring purposes. Line and path far end
block error indications (M0 or M1, G1) are also accumulated. The S/UNI-ULTRA
interprets the received payload pointers (H1, H2) and extracts the synchronous
payload envelope which carries the received ATM cell payload.
The S/UNI-ULTRA frames to the ATM payload using cell delineation. HCS error
correction is provided. Idle/unassigned cells may be dropped according to a
programmable filter. Cells are also dropped upon detection of an uncorrectable
header check sequence error. The ATM cell payloads are descrambled. Generic
flow control (GFC) bits from error free cells are extracted and presented on a
serial link for external processing.
Legitimate ATM cells are written to a four cell FIFO buffer. These cells are read
from the FIFO using a synchronous 8 bit wide datapath interface with cell-based
handshake. Counts of received ATM cell headers that are errored and
uncorrectable, those that are errored and correctable and all passed cells are
accumulated independently for performance monitoring purposes.
The S/UNI-ULTRA transmits SONET/SDH frames via a bit serial interface and
formats section, line, and path overhead appropriately. It performs framing
pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates
section, line, and path bit interleaved parity (B1, B2, B3) as required to allow
performance monitoring at the far end. Line and path far end block error
indications (M0 or M1, G1) are also inserted.
The S/UNI-ULTRA generates the payload pointer (H1, H2) and inserts the
synchronous payload envelope which carries the ATM cell payload. It supports
the insertion of a variety of errors into the transmit stream, such as framing
pattern errors, bit interleaved parity errors, and illegal pointers, which are useful
for system diagnostics.
ATM cells are written to an internal programmable-length 4-cell FIFO using a
synchronous 8 bit wide datapath interface. Idle/unassigned cells are
automatically inserted when the internal FIFO contains less than one cell or the
XOFF input is asserted. Generic flow control (GFC) bits may be inserted
downstream of the FIFO via a serial link so that all FIFO latency may be
bypassed. A transmission off (XOFF) input is provided to allow the suspension
of active ATM cell transmission independent of the FIFO fill state.
The S/UNI-ULTRA generates the header check sequence and scrambles the
payload of the ATM cells. Payload scrambling can be disabled.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 8

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