HN29V1G91T-30 데이터 시트보기 (PDF) - Renesas Electronics

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HN29V1G91T-30

128M × 8-bit AG-AND Flash Memory

Renesas Electronics 

HN29V1G91T-30

Random Data output in a Page Read

When the device output the data serially in Page read mode operation, the data from any column address in

a Page which is reading can be output by writing 05h and E0h with two column address cycles.

There is no restriction on an order of column address which can be specified and it is possible to specify

many times including same column address in the same Page address.

CLE

CE

WE

ALE

RE

I/O

R/B

Column Page

address L address N

00h CA1 CA2 RA1 RA2 30h

pageN

L L+1 L+2

Column

address M

05h CA1 CA2 E0h

pageN

M M+1 M+2

Memory array

Data register

L

Page N

M

Rev.4.00, Jun.20.2004, page 12 of 89

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