HT48R51 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT48R51

8-Bit Microcontroller Series

Holtek Semiconductor 

HT48CXX/HT48RXX

• Location 00CH

Location 00CH is reserved for the timer/ event

counter 1 interrupt service program of the

HT48C50/HT48C70 only. If the timer inter-

rupt results from a timer/event counter 1

overflow, the interrupt is enabled, and the

stack is not full, the program begins execution

at location 00CH.

• Table location

Any location in the ROM can be used as a

look–up table. The instructions TABRDC [m]

(the current page, 1 page=256 words) and

TABRDL [m] (the last page) transfer the con-

tents of the lower-order byte to the specified

data memory, and the higher-order byte to

TBLH (08H). Only the destination of the

lower-order byte in the table is well-defined,

and the higher-order byte of the table word is

transferred to the Table Higher-order byte

register (TBLH). The TBLH is read only. The

Table Pointer (TBLP), on the other hand, is a

read/write register (07H) used to indicate the

table location. Before accessing the table, the

location should be placed in the TBLP. The

TBLH is read only and cannot be restored. If

the main routine and the ISR (Interrupt Serv-

ice Routine) both employ the table read in-

struction, the contents of the TBLH in the

main routine is likely to be changed by the

table read instruction used in the ISR. Errors

will then occur. Hence, simultaneously using

the table read instruction in the main routine

and the ISR should be avoided. Nonetheless,

if the application of the table read instruction

Instruction(s)

*m~*8

∗7

∗6

TABRDC [m]

Pm~P8 @7

@6

TABRDL [m]

1~1

@7

@6

to both the main routine and the ISR cannot

be avoided, interrupts should be disabled

prior to the table read instruction, and they

should not be enabled until the TBLH is

backed-up. All the table related instructions

require 2 cycles to complete an operation.

These areas may function as a normal pro-

gram memory depending upon the user’s re-

quirements.

Stack register – STACK

The stack register is a special memory port used

to save the contents of the PC. The stack can be

organized into 2, 4, or 8 levels according to the

microcontroller selected (2 levels for the

HT48C10/HT48C30, 4 levels for the HT48C50,

8 levels for the HT48C70). The register is nei-

ther part of the data nor part of the program,

and is neither readable nor writeable. Any acti-

vated level is indexed by a stack pointer (SP)

and is neither readable nor writeable. At a sub-

routine call or interrupt acknowledgment, the

contents of the PC is pushed onto the stack. At

the end of a subroutine or an interrupt routine,

signaled by a return instruction (RET or RETI),

the contents of the PC is restored to its previous

value from the stack. After chip reset, the SP

will point to the top of the stack.

If the stack is full and a non-masked interrupt

takes place, the interrupt request flag is recorded

but the acknowledgment is still inhibited. After

the stack pointer is decremented (by RET or

RETI), the interrupt will be serviced. This feature

prevents the occurrence of stack overflow, allow-

Table Location

∗5

∗4

∗3

∗2

∗1

∗0

@5

@4

@3

@2

@1

@0

@5

@4

@3

@2

@1

@0

Notes: ∗m~∗0: Bits of table location

@7~@0: Bits of table pointer

Pm~P8: Bits of current

Program Counter

Table location

m=9 for the HT48C10

m=10 for the HT48C30

m=11 for the HT48C50

m=12 for the HT48C70

15

25th May ’99

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