HT48R51 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT48R51

8-Bit Microcontroller Series

Holtek Semiconductor 

HT48CXX/HT48RXX

On entering the interrupt sequence or execut-

ing the subroutine call, the status register will

not be automatically pushed onto the stack . If

the contents of the status is important and the

subroutine can corrupt the status register, the

programmer should take precautions to save it

properly.

Interrupt

The four microcontrollers all provide an exter-

nal interrupt and internal timer/event counter

interrupts. The interrupt control register

(INTC;0BH) contains interrupt control bits for

setting the enable/disable mode and the interrupt

request flags.

if the related interrupt is enabled, until the SP

is decremented. If immediate servicing is de-

sired, the stack should be prevented from be-

coming full.

All these interrupts have a wake-up capability.

As an interrupt is serviced, a control transfer

occurs by pushing the PC onto the stack and

then by branching it to subroutines at the speci-

fied location(s) in the ROM. Only the contents of

the PC can be pushed onto the stack. If the

contents of the register and of the status regis-

ter (STATUS) are altered by the interrupt serv-

ice program which corrupts the desired control

sequence, the programmer should save these

contents first.

Once an interrupt subroutine is serviced, the

remaining interrupts will all be blocked (by

clearing the EMI bit). This scheme may prevent

any further interrupt nesting. Other interrupt

requests may happen during this interval but

only the interrupt request flag will be recorded.

If a certain interrupt requires servicing within

the service routine, the programmer may set the

EMI bit and the corresponding bit of INTC so as

to allow interrupt nesting. If the stack is full, the

interrupt request will not be acknowledged, even

The external interrupt is triggered by a high to

low transition of the INT, and the related inter-

rupt request flag (EIF; bit 4 of INTC) is then set.

When the interrupt is enabled, the stack is not

full, and the external interrupt is active, a sub-

routine call to location 04H will occur. The inter-

rupt request flag (EIF) and EMI bits will also be

cleared to disable other interrupts.

Of the four microcontrollers, the internal

timer/event counter interrupt of the HT48C10/

HT48C30 is initialized by setting the timer/

Labels

C

Bits

0

Function

C is set if the operation results in a carry during an addition operation or if a

borrow does not take place during a subtraction operation; otherwise C is

cleared. Also it is affected by a rotate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or

AC

1 no borrow from the high nibble into the low nibble in subtraction; otherwise AC

is cleared.

Z

2

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is

cleared.

OV

3

OV is set if the operation results in a carry into the highest-order bit but not a

carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD

4

PD is cleared by either a system power-up or executing the CLR WDT

instruction. PD is set by executing the HALT instruction.

TO

5

TO is cleared by a system power-up or executing the CLR WDT or HALT

instruction. TO is set by a WDT time-out.

—

6 Undefined, read as 0

—

7 Undefined, read as 0

Status register

18

25th May ’99

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