HT48R51 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT48R51

8-Bit Microcontroller Series

Holtek Semiconductor 

HT48CXX/HT48RXX

event counter interrupt request flag (TF; bit 5 of

INTC), that is caused by a timer overflow. When

the interrupt is enabled, and the stack is not

full, and the TF bit is set, a subroutine call to

location 08H will occur. The related interrupt

request flag (TF) will be reset and the EMI bit

will be cleared to disable further interrupts.

The internal timer/event counter of the

HT48C50/HT48C70, is composed of two inter-

rupts, namely internal timer/event counter 0

interrupt and timer/event counter 1 interrupt.

The internal timer/event counter 0 interrupt is

initialized by setting the timer/event counter 0

interrupt request flag (T0F; bit 5 of INTC)

which is caused by a timer/event counter 0 over-

flow. After the interrupt is enabled, the stack is

not full, and the T0F bit is set, a subroutine call

to location 08H will occur. The related interrupt

request flag (T0F) will be reset and the EMI bit

be cleared to disable further interrupts. On the

other hand, the timer/event counter 1 interrupt

is operated in the same manner as the timer/

event counter 0. The related interrupt control

bits ET1I and T1F of the timer/event counter 1

are bit 3 and bit 6 of the INTC, respectively.

During the execution of an interrupt subroutine

of the four microcontrollers, other interrupt ac-

knowledgments are all held until the RETI in-

struction is executed or the EMI bit and the

related interrupt control bit are both set to 1

(when the stack is not full). To return from the

interrupt subroutine, the RET or RETI instruc-

tion may be invoked. The RETI will set the EMI

bit in order to enable an interrupt service

whereas the RET will not.

Interrupts that occur in an interval between the

rising edges of two consecutive T2 pulses are

serviced on the latter of the two T2 pulses if the

corresponding interrupts are enabled. In case of

simultaneous requests, the following table

shows the priority that is applied. These can be

masked by resetting the EMI bit.

No. Interrupt Source Priority Vector

a External interrupt

1

04H

b

Timer/event

counter 0 overflow

2

08H

*c

Timer/event

counter 1 overflow

3

0CH

* Note: c applies only to the HT48C50/ HT48C70

Register Bit No.

0

1

2

INTC

3

(0BH)

4

5

6

7

Label

EMI

EEI

ET0I

ET1I

EIF

T0F

T1F

—

Function

Control the master (global) interrupt

(1= enabled; 0= disabled)

Control the external interrupt

(1= enabled; 0= disabled)

Control the timer/event counter 0 interrupt

(1= enabled; 0= disabled)

Control the timer/event counter 1 interrupt (for the

HT48C50/HT48C70 only) (1= enabled; 0= disabled)

External interrupt request flag

(1= active; 0= inactive)

Internal timer/event counter 0 request flag

(1= active; 0= inactive)

Internal timer/event counter 1 request flag (for the

HT48C50/HT48C70 only) (1= active; 0= inactive)

Unused bit, read as “0”

INTC register

19

25th May ’99

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