HT48RXX 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT48RXX

8-Bit Microcontroller Series

Holtek Semiconductor 

HT48CXX/HT48RXX

The timer/event counter interrupt request flag

(TF), external interrupt request flag (EIF), en-

able timer/event counter bit (ETI), enable exter-

nal interrupt bit (EEI), and enable master

interrupt bit (EMI) constitute an interrupt con-

trol register (INTC) of the HT48C10/HT48C30

which is located at 0BH in the RAM. On the

other hand, the timer/event counter 0/1 inter-

rupt request flag (T0F/T1F), external interrupt

request flag (EIF), enable timer/event counter

0/1 bit (ET0I/ET1I), enable external interrupt

bit (EEI), and enable master interrupt bit (EMI)

make up the interrupt control register (INTC) of

the HT48C50/HT48C70 which is located at 0BH

in the RAM. EMI, EEI, and ETI, of the

HT48C10/HT48C30 or EMI, EEI, ET0I, and

ET1I of the HT48C50/HT48C70 are all used to

control the enable/disable status of interrupts.

These bits prevent the requested interrupt from

being serviced. Once the interrupt request flags

(TF, EIF of the HT48C10/HT48C30 or T0F, T1F,

EIF of the HT48C50/HT48C70) are set, they

will remain in the INTC register until the inter-

rupts are all serviced or cleared by a software

instruction.

It is suggested that a program should not em-

ploy the “CALL subroutine” within the inter-

rupt subroutine, since its operation within the

interrupt subroutine may damage the original

control sequence, and interrupts often occur in

an unpredictable manner or it may need imme-

diate servicing for certain applications. Given

this, if only one stack is left and enabling the

interrupt is not well controlled, the original con-

trol sequence may be ruined as a result of operating

the CALL subroutine in the interrupt subroutine.

Oscillator configuration

There are 2 oscillator circuits available, namely

RC oscillator and crystal oscillator, decided by

mask options. Both are designed for system

clocks. No matter what type of oscillator is cho-

sen, the signal supports the system clock. The

HALT mode stops the system oscillator and ig-

nores any external signals so as to conserve

power.

Of the two oscillator types, if an RC oscillator is

used, an external resistor between OSC1 and

System oscillator

VDD is required and its resistance ranges from

51kΩ to 1MΩ. The system clock, divided by 4, is

available on OSC2 (NMOS open drain output),

which can be used to synchronize external logic.

The RC oscillator provides the most cost effec-

tive solution. However, the frequency of the os-

cillation may vary with VDD, temperature and

the chip itself due to process variations. It is,

therefore, not suitable for timing sensitive op-

erations where accurate oscillator frequency is

desired. On the other hand, if the crystal oscil-

lator is used, a crystal across OSC1 and OSC2

is needed to provide the feedback and phase

shift required for the crystal oscillator. No other

external components are required. Instead of a

crystal, the resonator can also be connected be-

tween OSC1 and OSC2 to derive a frequency

reference, but two external capacitors in OSC1

and OSC2 are required.

The WDT oscillator is a free running on-chip RC

oscillator, and no external components are re-

quired. Even if the system enters the power

down mode, the system clock is stopped but the

WDT oscillator still works with a period of ap-

proximately 78 µs. The WDT oscillator can be

disabled by mask option to conserve power.

Watchdog timer – WDT

The clock source of the WDT is implemented by

a dedicated RC oscillator (WDT oscillator) or an

instruction clock (system clock divided by 4),

decided by mask options. The WDT is designed

to prevent a software malfunction or sequence

from jumping to an unknown location with un-

predictable results. The WDT can be disabled

by mask option. If the WDT is disabled, all the

executions related to the WDT may lead to no

operation.

20

25th May ’99

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