HT48R70A-1(2004) 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT48R70A-1
(Rev.:2004)

I/O Type 8-Bit MCU

Holtek Semiconductor 

HT48R70A-1/HT48C70-1

causes a device initialization and the WDT overflow per-

forms a ²warm reset². After the TO and PDF flags are

examined, the reason for chip reset can be determined.

The PDF flag is cleared by system power-up or execut-

ing the ²CLR WDT² instruction and is set when execut-

ing the ²HALT² instruction. The TO flag is set if the WDT

time-out occurs, and causes a wake-up that only resets

the PC and SP; the others remain in their original status.

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake-up the

device by options. Awakening from an I/O port stimulus,

the program will resume execution of the next instruc-

tion. If it awakens from an interrupt, two sequence may

occur. If the related interrupt is disabled or the interrupt

is enabled but the stack is full, the program will resume

execution at the next instruction. If the interrupt is en-

abled and the stack is not full, the regular interrupt re-

sponse takes place. If an interrupt request flag is set to

²1² before entering the HALT mode, the wake-up func-

tion of the related interrupt will be disabled. Once a

wake-up event occurs, it takes 1024 tSYS (system clock

period) to resume normal operation. In other words, a

dummy period will be inserted after a wake-up. If the

wake-up results from an interrupt acknowledge signal,

the actual interrupt subroutine execution will be delayed

by one or more cycles. If the wake-up results in the next

instruction execution, this will be executed immediately

after the dummy period is finished.

To minimize power consumption, all the I/O pins should

be carefully managed before entering the HALT status.

The RTC oscillator still runs in the HALT mode (if the

RTC oscillator is enabled).

Reset

There are three ways in which a reset can occur:

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a ²warm re -

set² that resets only the PC and SP, leaving the other cir-

cuits in their original state. Some registers remain un-

changed during other reset conditions. Most registers

are reset to the ²initial condition² when the reset condi-

tions are met. By examining the PDF and TO flags, the

program can distinguish between different ²chip resets².

TO PDF

RESET Conditions

0 0 RES reset during power-up

u u RES reset during normal operation

0 1 RES wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT wake-up HALT

Note: ²u² stands for ²unchanged²

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem reset (power-up, WDT time-out or RES reset) or the

system awakes from the HALT state.

VDD

RES

tS S T

S S T T im e - o u t

C h ip R e s e t

Reset Timing Chart

V DD

0 .0 1 m F *

100kW

RES

10kW

0 .1 m F *

Reset Circuit

Note: ²*² Make the length of the wiring, which is con-

nected to the RES pin as short as possible, to

avoid noise interference.

H A LT

W DT

W a rm R e s e t

RES

O SC1

SST

1 0 - b it R ip p le

C o u n te r

C o ld

R eset

S y s te m R e s e t

Reset Configuration

When a system reset occurs, the SST delay is added

during the reset period. Any wake-up from HALT will en-

able the SST delay.

An extra option load time delay is added during system

reset (power-up, WDT time-out at normal mode or RES

reset).

The functional unit chip reset status are shown below.

PC

000H

Interrupt

Disable

Prescaler

Clear

WDT

Clear. After master reset,

WDT begins counting

Timer/Event Counter Off

Input/Output Ports Input mode

SP

Points to the top of the stack

Rev. 1.60

14

June 9, 2004

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