HT48R10A-1 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT48R10A-1

I/O Type 8-Bit MCU

Holtek Semiconductor 

HT48R10A-1/HT48C10-1

fS Y S

M

(1 /2 ~ 1 /2 5 6 )

U

8 - s ta g e P r e s c a le r

fR T C

X

fIN T

8 -1 M U X

O p tio n s

TM 1

TM 0

P S C 2~P S C 0 TM R

TE

D a ta B u s

T im e r /E v e n t C o u n te r R e lo a d

P r e lo a d R e g is te r

TM 1

TM 0

P u ls e W id th

M e a s u re m e n t

M o d e C o n tro l

TO N

T im e r /E v e n t

C o u n te r

O v e r flo w

to In te rru p t

1 /2

BZ

BZ

Timer/Event Counter

The timer/event counter can generate PFD signal by us-

ing external or internal clock and PFD frequency is de-

termine by the equation fINT/[2´(256-N)].

There are 2 registers related to the timer/event counter;

TMR ([0DH]), TMRC ([0EH]). Two physical registers are

mapped to TMR location; writing TMR makes the start-

ing value be placed in the timer/event counter preload

register and reading TMR gets the contents of the

timer/event counter. The TMRC is a timer/event counter

control register, which defines some options.

The TM0, TM1 bits define the operating mode. The

event count mode is used to count external events,

which means the clock source comes from an external

(TMR) pin. The timer mode functions as a normal timer

with the clock source coming from the fINT clock. The

pulse width measurement mode can be used to count

the high or low level duration of the external signal

(TMR). The counting is based on the fINT clock.

In the event count or timer mode, once the timer/event

counter starts counting, it will count from the current

contents in the timer/event counter to FFH. Once over-

flow occurs, the counter is reloaded from the timer/event

counter preload register and generates the interrupt re-

quest flag (TF; bit 5 of INTC) at the same time.

In the pulse width measurement mode with the TON

and TE bits equal to one, once the TMR has received a

transient from low to high (or high to low if the TE bits is

²0²) it will start counting until the TMR returns to the orig-

inal level and resets the TON. The measured result will

remain in the timer/event counter even if the activated

transient occurs again. In other words, only one cycle

measurement can be done. Until setting the TON, the

cycle measurement will function again as long as it re-

ceives further transient pulse. Note that, in this operat-

ing mode, the timer/event counter starts counting not

according to the logic level but according to the transient

edges. In the case of counter overflows, the counter is

reloaded from the timer/event counter preload register

and issues the interrupt request just like the other two

modes. To enable the counting operation, the timer ON

bit (TON; bit 4 of TMRC) should be set to 1. In the pulse

width measurement mode, the TON will be cleared au-

tomatically after the measurement cycle is completed.

But in the other two modes the TON can only be reset by

instructions. The overflow of the timer/event counter is

one of the wake-up sources. No matter what the opera-

tion mode is, writing a 0 to ETI can disable the interrupt

service.

In the case of timer/event counter OFF condition, writ-

ing data to the timer/event counter preload register will

also reload that data to the timer/event counter. But if the

timer/event counter is turned on, data written to it will

only be kept in the timer/event counter preload register.

The timer/event counter will still operate until overflow oc-

curs. When the timer/event counter (reading TMR) is read,

the clock will be blocked to avoid errors. As clock blocking

may results in a counting error, this must be taken into con-

sideration by the programmer.

The bit0~bit2 of the TMRC can be used to define the

pre-scaling stages of the internal clock sources of

timer/event counter. The definitions are as shown. The

overflow signal of timer/event counter can be used to

generate PFD signals for buzzer driving.

Input/Output Ports

There are 21 bidirectional input/output lines in the

microcontroller, labeled from PA to PC, which are

mapped to the data memory of [12H], [14H] and [16H]

respectively. All of these I/O ports can be used for input

and output operations. For input operation, these ports

are non-latching, that is, the inputs must be ready at the

T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H

or 16H). For output operation, all the data is latched and

remains unchanged until the output latch is rewritten.

Each I/O line has its own control register (PAC, PBC,

PCC) to control the input/output configuration. With this

control register, CMOS output or Schmitt trigger input

with or without pull-high resistor structures can be re-

configured dynamically (i.e. on-the-fly) under software

control. To function as an input, the corresponding latch

of the control register must write ²1². The input source

also depends on the control register. If the control regis-

ter bit is ²1², the input will read the pad state. If the con-

trol register bit is ²0², the contents of the latches will

move to the internal bus. The latter is possible in the

²read-modify-write² instruction.

Rev. 1.90

14

November 4, 2005

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