HT48C10-1 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT48C10-1 Datasheet PDF : 38 Pages
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HT48R10A-1/HT48C10-1
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H and 17H.
After a chip reset, these input/output lines remain at high
levels or floating state (dependent on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H or
16H) instructions.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the de-
vice. The highest 3-bit of port C are not physically imple-
mented; on reading them a ²0² is returned whereas writing
then results in a no-operation. See Application note.
There is a pull-high option available for all I/O ports (byte
option). Once the pull-high option of an I/O port is se-
lected, all I/O lines have pull-high resistors. Otherwise,
the pull-high resistors are absent. It should be noted that
a non-pull-high I/O line operating in input mode will
cause a floating state.
The PB0 and PB1 are pin-shared with BZ and BZ signal,
respectively. If the BZ/BZ option is selected, the output
signal in output mode of PB0/PB1 will be the PFD signal
generated by timer/event counter overflow signal. The
input mode always remaining its original functions.
Once the BZ/BZ option is selected, the buzzer output
signals are controlled by PB0 data register only. The I/O
functions of PB0/PB1 are shown below.
PB0 I/O
I
I
I
I
OO
O
OOOOO
PB1 I/O
I OOO I
I
I
OOOOO
PB0 Mode
x
x
x
x CB
B
CBBBB
PB1 Mode
x
CBB
x
x
x
CCCBB
PB0 Data
PB1 Data
PB0 Pad Status
PB1 Pad Status
x
x
0
1
D
0
x
D
x
x
x
x
I
I
I
I D0
I
D
0
B
I
I
1
D0 0
1
0
1
x
D1 D
D
x
x
B
D0 0
B
0
B
I
D1 D
D
0
B
Note:
²I² input, ²O² output, ²D, D0, D1² data,
²B² buzzer option, BZ or BZ, ²x² don't care
²C² CMOS output
D a ta B u s
W r ite C o n tr o l R e g is te r
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
( P B 0 , P B 1 O n ly ) P B 0
B Z /B Z
R e a d D a ta R e g is te r
S y s te m W a k e -u p
( P A o n ly )
IN T fo r P C 0 O n ly
T M R fo r P C 1 O n ly
P C 3 /P C 4 I/O M o d e O n ly
C o n tr o l B it
PU
D
Q
CK Q
S
D a ta B it
DQ
CK Q
S
M
U
X
M
U
X
BZEN
( P B 0 , P B 1 O n ly )
V DD
P A 0~P A 7
P B 0~P B 7
P C 0~P C 4
O P 0~O P 7
Input/Output Ports
Rev. 1.90
15
November 4, 2005
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