AD7849AN 데이터 시트보기 (PDF) - Analog Devices

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AD7849AN

Serial Input, 14-Bit/16-Bit DAC

Analog Devices 

AD7849

t1

SCLK

t2

t3

SYNC

BIN/COMP

SDIN

(AD7849B/C/T)

DB15 (N)

DB0 (N)

t4

t5

DB15

(N+1)

DB0

(N+1)

SDOUT

(AD7849B/C/T)

t6

DB15 (N)

DB0 (N)

t4

t5

SDIN

(AD7849A)

DB13 (N) DB0 (N)

SDOUT

(AD7849A)

DB13

(N+1)

t6

DB0

(N+1)

DB13 (N) DB0 (N)

t7

LDAC, CLR

DCEN IS TIED PERMANENTLY HIGH

Figure 14. Timing Diagram (Daisy-Chain Mode)

Serial Data Loading Format (Daisy Chain Mode)

By connecting DCEN high, the daisy-chain mode is enabled.

This mode of operation is designed for multi-DAC systems

where several AD7849s may be connected in cascade. In this

mode, the internal gating circuitry on SCLK is disabled and a

serial data output facility is enabled. The internal gating signal

is permanently active (low) so that the SCLK signal is continu-

ously applied to the input shift register when SYNC is low. The

data is clocked into the register on each falling SCLK edge after

SYNC going low. If more than 16 clock pulses are applied, the

data ripples out of the shift register and appears on the

SDOUT line. By connecting this line to the SDIN input on the

next AD7849 in the chain, a multi-DAC interface may be con-

structed. Sixteen SCLK pulses are required for each DAC in the

system. Therefore the total number of clock cycles must equal

16 × N where N is the total number of devices in the chain.

When the serial transfer to all devices is complete, SYNC is

taken high. This prevents any further data being clocked into

the input register.

A continuous SCLK source may be used if it can be arranged

that SYNC is held low for the correct number of clock cycles.

Alternatively, a burst clock containing the exact number of clock

cycles may be used and SYNC taken high some time later.

When the transfer to all input registers is complete, a common

LDAC signal updates all DAC latches with the data in each in-

put register. All analog outputs are therefore updated simulta-

neously, 5 µs after the falling edge of LDAC.

Clear Function (CLR)

The clear function bypasses the input shift register and loads the

DAC Latch with all 0s. It is activated by taking CLR low. In all

ranges except the Offset Binary bipolar range (–5 V to +5 V) the

output voltage is reset to 0 V. In the offset binary bipolar range

the output is set to VREF–. This clear function is distinct and

separate from the automatic power-on reset feature of the device.

APPLYING THE AD7849

Power Supply Sequencing and Decoupling

In the AD7849, VCC should not exceed VDD by more than

0.4 V. If this does happen then an internal diode can be turned

on and produce latch-up in the device. Care should be taken to

employ the following power supply sequence: VDD; VSS; VCC.

In systems where it is possible to have an incorrect power

sequence (for example, if VCC is greater than 0.4 V while VDD is

still 0 V), the circuit of Figure 15 may be used to ensure that

the Absolute Maximum Ratings are not exceeded.

VDD

VCC

1N4148

SD103C

1N5711

1N5712

VDD

VCC

AD7849

Figure 15. Power Supply Protection

–10–

REV. B

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