AD7849AN 데이터 시트보기 (PDF) - Analog Devices
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AD7849AN Datasheet PDF : 15 Pages
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AD7849
Unipolar Configuration
Figure 16 shows the AD7849 in the unipolar binary circuit con-
figuration. The DAC is driven by the AD586, +5 V reference.
Since ROFS is tied to 0 V, the output amplifier has a gain of ×2
and the output range is 0 V to +10 V. If a 0 V to +5 V range is
required, ROFS should be tied to VOUT, configuring the output
stage for a gain of ×1. Table I gives the code table for the circuit
of Figure 16.
+15V +5V
2
8
6
AD586
5
C1
1nF
4
R1
10kΩ
SIGNAL GND
*ADDITIONAL PINS
OMITTED FOR CLARITY
VDD
VCC
VREF+
VOUT
ROFS
AD7849*
AGND
VREF–
DGND
VSS
–15V
VOUT
(0 TO +10V)
Figure 16. Unipolar Binary Operation
Table I. Code Table for Figure 16
Binary Number in DAC Latch
MSB
LSB
Analog Output
(VOUT)
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
+10 (65535/65536) V
+10 (32768/65536) V
+10 (1/65536) V
0V
NOTE: Assumes 16-bit resolution; 1 LSB = 10 V/216 = 10 V/65536 = 152 µV.
Offset and gain may be adjusted in Figure 16 as follows: To ad-
just offset, disconnect the VREF– input from 0 V, load the DAC
with all 0s and adjust the VREF– voltage until VOUT = 0 V. For
gain adjustment, the AD7849 should be loaded with all 1s and
R1 adjusted until VOUT = 10 (65535)/65536 = 9.9998474 V,
(B, T and C, 16-bit versions). For the 14-bit A version, VOUT
should be 10 (16383/16384) = 9.9993896 V.
If a simple resistor divider is used to vary the VREF– voltage, it is
important that the temperature coefficients of these resistors match
that of the DAC input resistance (–300 ppm/°C). Otherwise, extra
offset errors will be introduced over temperature. Many circuits
will not require these offset and gain adjustments. In these cir-
cuits, R1, can be omitted. Pin 5 of the AD586 may be left open
circuit and Pin 2 (VREF– ) of the AD7849 tied to 0 V.
Bipolar Configuration
Figure 17 shows the AD7849 set up for ± 10 V bipolar opera-
tion. The AD588 provides precision ± 5 V tracking outputs
which are fed to the VREF+ and VREF– inputs of the AD7849.
The code table for Figure 17 is shown in Table II.
Full-scale and bipolar-zero adjustment are provided by varying
the gain and balance on the AD588. R2 varies the gain on the
AD588 while R3 adjusts the +5 V and –5 V outputs together
with respect to ground.
+15V +5V
C1
1µF
R2
100kΩ
R3
100kΩ
R1
39kΩ
46
7
2
3
9
1
AD588
5
14
10
15
11
16
12 8 13
VDD
VCC
VOUT
VREF+
ROFS
AD7849*
AGND
VREF– DGND
VSS
*ADDITIONAL PINS
OMITTED FOR CLARITY
–15V
VOUT
(–10V TO +10V)
SIGNAL
GND
Figure 17. Bipolar ±10 V Operation
Table II. Offset Binary Code Table for Figure 17
Binary Number in DAC Latch
MSB
LSB
Analog Output
(VOUT)
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
+10 (32767/32768) V
+10 (1/32768) V
0V
–10 (1/32768) V
–10 (32768/32768) V
NOTE: Assumes 16-bit resolution; 1 LSB = 20 V/216 = 305 µV.
For bipolar-zero adjustment on the AD7849, load the DAC
with 100 . . . 000 and adjust R3 until VOUT = 0 V. Full scale is
adjusted by loading the DAC with all 1s and adjusting R2 until
VOUT = 9.999694 V.
When bipolar-zero and full-scale adjustment are not needed, R2
and R3 can be omitted, Pin 12 on the AD588 should be con-
nected to Pin 11 and Pin 5 should be left floating.
If a user wants a ± 5 V output range with the circuit of Figure
17, simply tie Pin 20 (ROFS) to Pin 19 (VOUT), thus reducing the
output gain stage to unity and giving an output range of ± 5 V.
REV. B
–11–
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