AD7849AN 데이터 시트보기 (PDF) - Analog Devices
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AD7849AN Datasheet PDF : 15 Pages
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AD7849
RESET SPECIFICATIONS (These specifications apply when the device goes into the Reset mode during a power-up or
power-down sequence.) VOUT unloaded.
Parameter
All Versions Units
Test Conditions/Comments
VA1, Low Threshold Voltage for VDD, VSS 1.2
0
VB, High Threshold Voltage for VDD, VSS 9.5
6.4
VC, Low Threshold Voltage for VCC
1
0
VD, High Threshold Voltage for VCC
4
2.5
G2 RON
1
Volt max
Volts typ
Volts max
Volts min
Volt max
Volts typ
Volts max
Volts min
kΩ typ
This is the lower VDD/VSS threshold voltage for the reset
function. Above this, the reset is activated.
This is the higher VDD/VSS threshold voltage for the reset
function. Below this, the reset is activated. Typically 8 volts.
This is the lower threshold voltage for the reset function.
Above this, the reset is activated.
This is the higher VCC threshold voltage for the reset function.
Below this, the reset is activated. Typically 3 volts.
On Resistance of G2; VDD = 2 V; VSS = –2 V; IG2 = 1 mA.
NOTES
1A pull-down resistor (65 kΩ) on VOUT maintains 0 V output when VDD/VSS is below VA.
Specifications subject to change without notice.
AC PERFORMANCE CHARACTERISTICS (These characteristics are included for Design Guidance and are not
subject to test. (VREF+ = +5 V; VDD = +14.25 V to +15.75 V; VSS = –14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V; ROFS connected to 0 V.)
Parameter
T
Version
A, B, C
Versions Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Settling Time1
7
10
Slew Rate
4
Digital-to-Analog Glitch Impulse 250
150
AC Feedthrough
1
Digital Feedthrough
5
Output Noise Voltage Density
1 kHz–100 kHz
80
7
µs typ
To 0.006% FSR. VOUT Loaded. VREF– = 0 V.
10
µs typ
To 0.003% FSR. VOUT Loaded. VREF– = –5 V.
4
V/µs typ
250
nV-s typ
DAC Alternately Loaded with 00 . . . 00 and
111 . . . 11. VOUT Unloaded. LDAC Perma-
nently Low. BIN/COMP Set to 1. VREF– = –5 V.
150
nV-s typ
LDAC Frequency = 100 kHz
1
mV pk-pk typ VREF– = 0 V, VREF+ = 1 V rms, 10 kHz Sine Wave.
DAC Loaded with All 0s. BIN/COMP Set to 0.
5
nV-s typ
DAC Alternately Loaded with All 1s and All 0s.
SYNC High.
80
nV/√Hz typ
Measured at VOUT. VREF+ = VREF– = 0 V.
BIN/COMP Set to 0.
NOTES
1LDAC = 0. Settling time does not include deglitching time of 5 µs (typ).
Specification subject to change without notice.
TIMING CHARACTERISTICS1, 2 (VDD = +14.25 V to +15.75 V; VSS = –14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V;
RL = 2 kΩ, CL = 200 pF. All Specifications TMIN to TMAX unless otherwise noted.)
Parameter
Limit at +25؇C
(All Versions)
Limit at TMIN, TMAX
(All Versions)
Units
t13
200
200
t2
50
50
t3
70
70
t4
10
10
t5
40
40
t64
80
80
t7
80
80
tr
30
30
tf
30
30
ns min
ns min
ns min
ns min
ns min
ns max
ns min
µs max
µs max
NOTES
1Guaranteed by characterization.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3SCLK mark/space ratio range is 40/60 to 60/40.
4SDO load capacitance is 50 pF.
Specification subject to change without notice.
Conditions/Comments
SCLK Cycle Time
SYNC to SCLK Setup Time
SYNC to SCLK Hold Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SDO Valid
LDAC, CLR Pulsewidth
Digital Input Rise Time
Digital Input Fall Time
REV. B
–3–
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