AD7849AN 데이터 시트보기 (PDF) - Analog Devices

부품명

상세내역

제조사

AD7849AN

Serial Input, 14-Bit/16-Bit DAC

Analog Devices 

AD7849

TERMINOLOGY

Least Significant Bit

This is the analog weighting of 1 bit of the digital word in a DAC.

For the AD7849, B, C and T versions, 1 LSB = (VREF+ – VREF–)/

216. For the AD7849, A version, 1 LSB = (VREF+ – VREF–)/214.

Relative Accuracy

Relative accuracy or endpoint nonlinearity is a measure of the

maximum deviation from a straight line passing through the

endpoints of the DAC transfer function. It is measured after

adjusting for both endpoints (i.e., offset and gain errors are ad-

justed out) and is normally expressed in least significant bits or

as a percentage of full-scale range.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured

change and the ideal change between any two adjacent codes. A

specified differential nonlinearity of less than ± 1 LSB over the

operating temperature range ensures monotonicity.

Gain Error

Gain error is a measure of the output error between an ideal

DAC and the actual device output with all 1s loaded after offset

error has been adjusted out. Gain error is adjustable to zero

with an external potentiometer.

Offset Error

This is the error present at the device output with all 0s loaded

in the DAC. It is due to op amp input offset voltage and bias

current and the DAC leakage current.

Bipolar Zero Error

When the AD7849 is connected for bipolar output and

(100 . . . 000) is loaded to the DAC, the deviation of the analog

output from the ideal midscale of 0 V, is called the bipolar zero

error.

Digital-to-Analog Glitch Impulse

This is the amount of charge injected from the digital inputs to

the analog output when the inputs change state. This is nor-

mally specified as the area of the glitch in nV-secs.

Multiplying Feedthrough Error

This is an ac error due to capacitive feedthrough from either of

the VREF terminals to VOUT when the DAC is loaded with all 0s.

Digital Feedthrough

When the DAC is not selected (SYNC is held high), high fre-

quency logic activity on the digital inputs is capacitively coupled

through the device to show up as noise on the VOUT pin. This

noise is digital feedthrough.

PIN FUNCTION DESCRIPTION

Pin Mnemonic Description

1

VREF+

2

VREF–

3

VSS

4 SYNC

VREF+ Input. The DAC is specified for VREF+ of +5 V. The DAC is fully multiplying so that the VREF+ range is +5 V to –5 V.

VREF– Input. The DAC is specified for VREF– of –5 V. Since the DAC is fully multiplying the VREF– range is –5 V to +5 V.

Negative supply for the analog circuitry. This is nominally –15 V.

Data Synchronization Logic Input. When it goes low, the internal logic is initialized in readiness for a new data word.

5 SCLK

Serial Clock Logic Input. Data is clocked into the input register on each SCLK falling edge.

6

VCC

7 SDOUT

Positive supply for the digital circuitry. This is nominally +5 V.

Serial Data Output. With DCEN at Logic “1,” this output is enabled and the serial data in the input shift register is

clocked out on each rising edge of SCLK.

8 DCEN

Daisy-Chain Enable Logic Input. Connect this pin high if a daisy-chain interface is being used, otherwise this pin must be

connect low.

9 BIN/COMP Logic Input. This input selects the data format to be either binary or 2s complement. In the unipolar output range,

natural binary format is selected by connecting the input to a Logic “0.” In the bipolar output range, offset binary is

selected by connecting this input to a Logic “0” and 2s complement is selected by connecting it to a Logic “1.”

10 DGND

11 LDAC

Digital Ground. Ground reference point for the on-chip digital circuitry.

Load DAC Logic Input. This input updates the DAC output. The DAC output is updated on the falling edge of this

signal or alternatively, if this input is permanently low, an automatic update mode is selected whereby the DAC is updated

on the 16th falling SCLK edge.

12 SDIN

13 CLR

14 RSTIN

15 RSTOUT

Serial Data Input. The 16-bit serial data word is applied to this input.

Clear Logic Input. Taking this input low sets VOUT to 0 V in both the unipolar output range and the bipolar 2s comple-

ment output range. It sets VOUT to VREF– in the offset binary bipolar output range.

Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic “0” to this input, resets

the DAC output to 0 V. In normal operation it should be tied to Logic “1.”

Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. It may used to control

other system components if desired.

16 AGND

This is the analog ground for the device. It is the point to which the output gets shorted in the reset mode.

17 VDD

18 NC

Positive supply for the analog circuitry. This is +15 V nominal.

No Connect. Leave unconnected.

19

VOUT

20

ROFS

DAC Output Voltage Pin.

Input to summing resistor of DAC output amplifier. This is used to select output voltage ranges. See Figures 16 to 19

in “APPLYING THE AD7849.”

REV. B

–5–

Share Link: