IMC004FLSA-15 데이터 시트보기 (PDF) - Intel

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IMC004FLSA-15

SERIES 2 FLASH MEMORY CARDS

Intel 

SERIES 2 FLASH MEMORY CARDS

Erase Setup Erase Confirm

Commands (20H)

Within a device a two-command sequence initiates

an erase operation on one device block at a time

After the system switches VPP to VPPH an Erase

Setup command (20H) prepares the CUI for the

Erase Confirm command (D0H) The device’s WSM

controls the erase algorithms internally After receiv-

ing the two-command erase sequence the device

automatically outputs Status Register data when

read (see Figure 14) If the command after erase

setup is not an Erase Confirm command the CR

sets the Write Failure and Erase Failure bits of the

Status Register places the device into the Read

Status Register mode and waits for another com-

mand The Erase Confirm command enables the

WSM for erase (simultaneously closing the address

latches for that device’s block (A16 – A19) The CPU

detects the completion of the erase operation by an-

alyzing card-level or device-level indicators Card-

level indicators include the RDY BSY pin and the

READY-BUSY STATUS REGISTER while device-

level indicators include the specific device’s Status

Register Only the Read Status Register and Erase

Suspend command is valid during an active erase

operation Upon completion of the erase sequence

(see section on Status Register) the device’s Status

Register reflects the result of the erase operation

The device remains in the Read Status Register

mode until the CUI receives an alternate command

The two-step block-erase sequence ensures that

memory contents are not accidentally erased Erase

attempts while VPPL k VPPk VPPH produce spuri-

ous results and are not recommended Reliable

block erasure only occurs when VPP e VPPH In the

absence of this voltage memory contents are pro-

tected against erasure If block erase is attempted

while VPP e VPPL the VPP Status bit will be set to

‘‘1’’

When erase completes the Erase Status bit should

be checked If an erase error is detected the de-

vice’s Status Register should be cleared The CUI

remains in Read Status Register mode until receiv-

ing an alternate command

Erase Suspend (B0H) Erase Resume

(D0H)

Erase Suspend allows block erase interruption to

read data from another block of the device or to

temporarily conserve power for another system op-

eration Once the erase process starts writing the

Erase Suspend command to the CUI (see Figure 15)

requests the WSM to suspend the erase sequence

at a predetermined point in the erase algorithm In

the erase suspend state the device continues to

output Status Register data when read

Polling the device’s RY BY and Erase Suspend

Status bits (Status Register) will determine when the

erase suspend mode is valid It is important to note

that the card’s RDY BSY pin will also transition to

VOH and will generate an interrupt if this pin is con-

nected to a system-level interrupt At this point a

Read Array command can be written to the device’s

CUI to read data from blocks other than those

which are suspended The only other valid com-

mands at this time are Read Status Register (70H)

and Erase Resume (D0H) If VPP goes low during

Erase Suspend the VPP Status bit is set in the

Status Register and the erase operation is aborted

The Erase Resume command clears the Erase Sus-

pend state and allows the WSM to continue with the

erase operation The device’s RY BY Status and

Erase Suspend Status bits and the card’s READY-

BUSY Status Register are automatically updated to

reflect the erase resume condition The card’s RDY

BSY pin also returns to VOL

Invalid Reserved

These are unassigned commands having the same

effect as the Read Array command Do not issue

any command other than the valid commands speci-

fied above Intel reserves the right to redefine these

codes for future functions

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