KK82C55A
READ TIMING
A0-1,CS
tAR
DATA BUS
HIGH IMPEDANCE
tRD
RD
VALID
tRA
HIGH IMPEDANCE
tDR
tRR
A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT
2.4
2.0
2.0
TEST POINTS
CL=150pF
0.45
0.8
0.8
A.C. Testing Inputs Are Driven At 2.4V For A Logic 1 And 0.45V
For A Logic 0 Timing Measurements Are Made At 2.0V For A Logic 1
And 0.8 For A Logic 0.
A.C. TESTING LOAD CIRCUIT
DEVICE
UNDER
TEST
CL=150pF
VEXT*
*VEXT Is Set At Various Voltages During Testing To
Guarantee The Specification. C L Includes Jig Capacitance.
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