MAX17409 데이터 시트보기 (PDF) - Maxim Integrated

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MAX17409

1-Phase Quick-PWM GPU Controller

Maxim Integrated 

1-Phase Quick-PWM GPU Controller

Output-Voltage Transition Timing

The MAX17409 performs mode transitions in a controlled

manner, automatically minimizing input surge currents.

This feature allows the circuit designer to achieve nearly

ideal transitions, guaranteeing just-in-time arrival at the

new output voltage level with the lowest possible peak

currents for a given output capacitance.

At the beginning of an output-voltage transition, the

MAX17409 blanks both PWRGD thresholds, preventing

the PWRGD open-drain output from changing states

during the transition. The controller enables the

PWRGD thresholds approximately 20µs after the slew-

rate controller reaches the target output voltage. The

slew rate is set to 12.5mV/µs to ensure that the transi-

tion can be completed within a reasonable time period.

The MAX17409 automatically controls the current to the

minimum level required to complete the transition in the

calculated time. The slew-rate controller uses an inter-

nal capacitor and current source to transition the target

voltage. The total transition time depends on the

12.5mV/µs slew rate, the voltage difference, and the

accuracy of the slew-rate controller, CSLEW, accuracy).

The slew rate is not dependent on the total output

capacitance, as long as the surge current is less than

the current limit. For all dynamic VID transitions, the

transition time (tTRAN) is given by:

t TRAN

=

VNEW - VOLD

12.5m Vµ s

where VOLD is the original output voltage, and VNEW is

the new target voltage. See Slew-Rate Accuracy in the

Electrical Characteristics for slew-rate limits. For soft-

start and shutdown, the controller automatically

reduces the slew rate to 1.56mV/µs (1/8 of the nominal

slew rate).

The output voltage tracks the slewed target voltage,

making the transitions relatively smooth. The average

inductor current required to make an output voltage

transition is:

IL ≅ COUT × 12.5mVµs

where COUT is the total output capacitance.

OVP LEVEL

HIGH VID

CPU CORE

VOLTAGE

VID (G0–G5)

SKIP

INTERNAL

PWM CONTROL

DH

OVP = 1.45V MIN

INTERNAL

TARGET

ACTUAL VOUT

SLEEP VID

PULSE-SKIPPING MODE

NO PULSES: VOUT > VTARGET

PWRGD

BLANK HIGH-Z

LOW THRESHOLD ONLY

tBLANK

20µs TYP

Figure 4. VID Transition

OVP TRACKS INTERNAL TARGET

NEW ACTIVE

VID

LOW VID

FORCED-PWM MODE

BLANK HIGH-Z

tBLANK

20µs TYP

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