MAX5003 데이터 시트보기 (PDF) - Maxim Integrated
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MAX5003 Datasheet PDF : 16 Pages
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High-Voltage PWM
Power-Supply Controller
where:
RMAXTON = Resistor between the MAXTON pin and
ground
VMIN = Minimum power-line voltage
VUVL = Power-line trip voltage
DCMAX(VMIN) = Maximum duty cycle at minimum
power-line voltage
For this application circuit, a 10% margin is reason-
able, so the value used is 50kΩ. This gives a maxi-
mum duty cycle of 50%. The maximum duty cycle
can now be expressed as:
DC(VCON,VIN )
=
VCON
-
0.5V
2.0V
VMIN
VIN
ƒSW
ƒNOM
×
DC MAX(VMIN)
≈
VCON
-
0.5V
2.0V
36V
VIN
ƒSW
ƒNOM
50%
where:
VCON = Voltage at the CON pin, input of the PWM
comparator
DC(VCON, VIN) = Duty cycle, function of VCON and
VIN
0.5V and 2.5V are the values at the beginning and
end of the PWM ramp.
The term ƒSW / ƒNOM varies from 0.8 to 1.2 to allow
for clock frequency variation. If the clock is running
at 300kHz and the input voltage is fixed, then the
duty cycle is a scaled portion of the maximum duty
cycle, determined by VCON.
DC(VCON, VMIN)
=
VCON
-
0.5V
50%
2.0V
DC(VCON, VMAX )
=
VCON
-
0.5V
25%
2.0V
DC(2.5V,VMIN) = 50%
DC(2.5V,VMAX ) = 25%
DC(0.5V,VMIN) = 0
DC(0.5V,VMAX ) = 0
7) Low-ESR/ESL ceramic capacitors were used in this
application. The output filter is made by two 22µF
ceramic capacitors in parallel. Normally, the ESR of
a capacitor is a dominant factor determining the rip-
ple, but in this case it is the capacitor value.
Calculating
IOUT =
1A
= 76mV
ƒSW × C 300kHz × 44µF
the ripple will be a fraction of this depending on the
duty cycle. For a 50% duty cycle, the ripple due to
the capacitance is approximately 45mV.
8)The PWM gain can be calculated from:
APWM = dVOUT =
dVCON
2
×
RL
LPRI
× ƒSW
VMIN
2.0V
DCMAX(VMI
=
2
×
RL
LPRI
× ƒSW
36V
2.0V
50%
≅3
Note that while the above formula incorporates the
product of the maximum duty cycle and VIN, it is
independent of VIN. For 1A output (RL = 5Ω), the
PWM gain is +3.0V/V. For a 10% load (RL = 50Ω),
the gain is multiplied by the square root of 10 and
becomes +10V/V. The pole of the system due to the
output filter is 1 / 2πRC, where R is the load resis-
tance and C the filter capacitor. Choosing a capaci-
tor and calculating the pole frequency by:
ƒP =
1
2π × RL × CL
=
1
2π
×
5Ω
×
44µF
it is 723Hz at full load. At 10% load it will be 72Hz,
since the load resistor is then 50Ω instead of 5Ω. The
total loop gain is equal to the PWM gain times the
gain in the combination of the voltage divider and
the error amplifier. The worst case for phase margin
is at full load. For a phase margin of 60 degrees, this
midband gain (G) must be set to be less than:
G<
ƒUErrorAmp
=
1 MHz
tan(PM) × APWM × ƒP 1.7 × 3 × 723Hz
where:
ƒU = Unity-gain frequency of error amplifier
PM = Phase margin angle
The DC accuracy of the regulator is a function of the
DC gain. For 1% accuracy, a DC gain of 20 is required.
Since the maximum midband gain for a stable
response is 16, an integrator with a flat midband gain
given by a zero is used. The midband gain is less than
16, to preserve stability, and the DC gain is much larger
than 20, to achieve high DC accuracy.
Optimization on the bench showed that a midband gain
of 5 gave fast transient response and settling with no
ringing. The zero was pushed as high in frequency as
possible without losing stability. The zero must be a
factor of two or so below the system unity-gain frequen-
cy (crossover frequency) at minimum load. With the
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