MAX767EAP(1994) 데이터 시트보기 (PDF) - Maxim Integrated

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MAX767EAP
(Rev.:1994)

5V-to-3.3V, Synchronous, Step-Down Power-Supply Controller

Maxim Integrated 

5V-to-3.3V, Synchronous, Step-Down

Power-Supply Controller

Place R1 as close as possible to the MAX767, prefer-

ably less than 10mm. Run the traces at minimum spac-

ing from one another. If they are longer than 20mm,

bypass CS to FB with a 1nF capacitor placed as close

as possible to these pins. The wiring layout for these

traces is critical for stable, low-ripple outputs (see

Layout and Grounding section).

Input Filter Capacitor, C1

Use at least 6µF per watt of output power for C1. If the

5V input is some distance away or comes through a PC

bus, greater capacitance may be desirable to improve

the load-transient response. Use a low-ESR capacitor

located no further than 10mm from the MOSFET switch

(N1) to prevent ringing. The ripple current rating must

be at least IRMS = 0.5 x IOUT. For high-current applica-

tions, two or more capacitors in parallel may be needed

to meet these requirements.

The ESR of C1 is effectively in series with the input. The

resistive dissipation of C1, IRMS2 x ESRC1, can signifi-

cantly impact the circuit’s efficiency.

Output Filter Capacitor, C2

The output filter capacitor determines the loop stability,

output voltage ripple, and output load-transient

response.

Stability

To ensure stability, stay above the minimum capaci-

tance value and below the maximum ESR value. These

values are:

C2 > —3Ω— µF

R1

and

ESRC2 < R1

Be sure to satisfy both these requirements. To achieve

the low ESR required, it may be appropriate to parallel

two or more capacitors and/or use a total capacitance

2 or 3 times larger than the calculated minimum.

Output Ripple

The output ripple in continuous-conduction mode is:

VOUT(RPL) = IOUT(max) x LIR x

(ESRC2

+

————1 ———)

2 x π x f x C2

where f is the switching frequency (200kHz or 300kHz).

In idle-mode, the ripple has a capacitive and a resistive

component:

.

VOUT(RPL) (C) = __0_._0_0_0_4__x_L___ x 0.89 Volts

R12 x C2

VOUT(RPL) (R) = 0_._0_2__x_E__S_R_C_2__

R1

The total ripple, VOUT(RPL), can be approximated as

follows:

if

VOUT(RPL) (R) < 0.5 VOUT(RPL) (C)

then

VOUT(RPL) = VOUT(RPL)(C)

otherwise

VOUT(RPL) = 0.5 VOUT(RPL) (C) +

VOUT(RPL) (R)

Load-Transient Performance

In response to a large step increase in load current, the

output voltage will sag for several microseconds unless

C2 is increased beyond the values that satisfy the

above requirements. Note that an increase in capaci-

tance is all that’s required to improve the transient

response, and that the ESR requirements don’t change.

Therefore, the added capacitance can be supplied by

an additional low-cost bulk capacitor in parallel with the

normal low-ESR switching-regulator capacitor. The

equation for voltage sag under a step load change is:

VSAG = ___________I_S_T_E_P_2_x__L_____________

2 x C2 x (VIN(min) x DMAX - 3.3V)

where DMAX is the maximum duty cycle. Higher duty

cycles are possible when the oscillator frequency is

reduced to 200kHz, since fixed propagation delays

through the PWM comparator become a lesser part of

the whole period. The tested worst-case limit for DMAX

is 92% at 200kHz or 89% at 300kHz. Lower inductance

values can reduce the filter capacitance requirement,

but only at the expense of increased output ripple (due

to higher peak currents).

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