MBM29LV008BA-70 데이터 시트보기 (PDF) - Fujitsu

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MBM29LV008BA-70

FLASH MEMORY CMOS 8M (1M × 8) BIT

Fujitsu 

MBM29LV008TA-70/-90/-12/MBM29LV008BA-70/-90/-12

Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase

Algorithm command sequence the devices will automatically program and verify the entire memory for an all

zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any

controls or timings during these operations.

The automatic erase begins on the rising edge of the last write pulse in the command sequence and terminates

when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read the

mode.

Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)

Figure 18 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.

Sector Erase

Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector

address (any address location within the desired sector) is latched on the falling edge of write pulse, while the

command (Data=30H) is latched on the rising edge of write pulse. After time-out of 50 µs from the rising edge

of the last sector erase command, the sector erase operation will begin.

Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 6. This sequence

is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently

erased. The time between writes must be less than 50 µs otherwise that command will not be accepted and

erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this

condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs

from the rising edge of the last write pulse will initiate the execution of the Sector Erase command(s). If another

falling edge of the write pulse occurs within the 50 µs time-out window the timer is reset. (Monitor DQ3 to determine

if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than

Sector Erase or Erase Suspend during this time-out period will reset the devices to the read mode, ignoring the

previous command string. Resetting the devices once execution has begun will corrupt the data in the sector.

In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status

section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and

with any number of sectors (0 to 18).

Sector erase does not require the user to program the devices prior to erase. The devices automatically program

all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing

a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any

controls or timings during these operations.

The automatic sector erase begins after the 50 µs time out from the rising edge of the write pulse pulse for the

last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status

section.) at which time the devices return to the read mode. Data polling must be performed at an address within

any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time

(Preprogramming)] × Number of Sector Erase

Figure 18 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.

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