MC10H330 데이터 시트보기 (PDF) - ON Semiconductor
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MC10H330 Datasheet PDF : 8 Pages
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MC10H330
Quad Bus Driver/Receiver
with 2-to-1 Output
Multiplexers
The MC10H330 is a Quad Bus Driver/Receiver with two–to–one
output multiplexers. These multiplexers have a common select and
output enable. When disabled, (OE = high) the bus outputs go to –2.0
V. Their output can be brought to a low state (VOL) by applying a high
level to the receiver enable (RE = High). The parameters specified are
with 25 Ω loading on the bus drivers and 50 Ω loads on the receivers.
• Propagation Delay, 1.5 ns Typical Data–to–Output
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
DIP
PIN ASSIGNMENT
VCC
1
XBUS
2
WBUS
3
VCC0
4
X1
5
X0
6
W1
7
W0
8
S
9
WIN
10
XIN
11
VEE
12
24
VCC0
23
YBUS
22
ZBUS
21
OE
20
Y0
19
Y1
18
Z0
17
Z1
16
RE
15
ZIN
14
YIN
13
VCC0
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
NOTE:
Each MECL 10H series circuit has been designed
to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed
circuit board and transverse air flow greater than
500 Ifpm is maintained. Receiver outputs are
terminated through a 50–ohm resistor to –2.0 volts
dc. Bus outputs are terminated through a 25–ohm
resistor to –2.0 volts dc.
http://onsemi.com
CDIP–24
L SUFFIX
CASE 758
MARKING
DIAGRAMS
24
MC10H330L
AWLYYWW
1
PDIP–24
P SUFFIX
CASE 724
24
MC10H330P
AWLYYWW
1
1
PLCC–28
FN SUFFIX
CASE 776
10H330
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10H330L
CDIP–24
15 Units/Rail
MC10H330P
PDIP–24
15 Units/Rail
MC10H330FN PLCC–28
37 Units/Rail
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 6
Publication Order Number:
MC10H330/D
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