MC33580BAPNA/R2 데이터 시트보기 (PDF) - Freescale Semiconductor

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MC33580BAPNA/R2

Quad High-Side Switch (Quad 15 mΩ)

Freescale Semiconductor 

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless

otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

SPI INTERFACE CHARACTERISTICS

Maximum Frequency of SPI Operation

f SPI

–

Required Low State Duration for RST (26)

t WRST

–

Rising Edge of CS to Falling Edge of CS (Required Setup Time) (27)

t CS

–

Rising Edge of RST to Falling Edge of CS (Required Setup Time) (27)

t ENBL

–

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (27)

t LEAD

–

Required High State Duration of SCLK (Required Setup Time) (27)

t WSCLKh

–

Required Low State Duration of SCLK (Required Setup Time) (27)

t WSCLKl

–

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (27)

t LAG

–

SI to Falling Edge of SCLK (Required Setup Time) (28)

t SI (SU)

–

Falling Edge of SCLK to SI (Required Setup Time) (28)

t SI (HOLD)

–

SO Rise Time

CL = 200 pF

t RSO

–

SO Fall Time

CL = 200 pF

SI, CS, SCLK, Incoming Signal Rise Time (28)

SI, CS, SCLK, Incoming Signal Fall Time (28)

Time from Falling Edge of CS to SO Low Impedance (29)

Time from Rising Edge of CS to SO High Impedance (30)

Time from Rising Edge of SCLK to SO Data Valid (31)

0.2 VDD ≤ SO ≤ 0.8 VDD, CL = 200 pF

t FSO

–

t RSI

–

t FSI

–

t SO(EN)

–

t SO(DIS)

–

t VALID

–

–

3.0

MHz

50

350

ns

–

300

ns

–

5.0

µs

50

167

ns

–

167

ns

–

167

ns

50

167

ns

25

83

ns

25

83

ns

ns

25

50

ns

25

50

–

50

ns

–

50

ns

–

145

ns

65

145

ns

ns

65

105

Notes

26. RST low duration measured with outputs enabled and going to OFF or disabled condition.

27. Maximum setup time required for the 33580 is the minimum guaranteed time needed from the microcontroller.

28. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

29. Time required for output status data to be available for use at SO. 1.0 kΩ on pullup on CS.

30. Time required for output status data to be terminated at SO. 1.0 kΩ on pullup on CS.

31. Time required to obtain valid data out from SO following the rise of SCLK.

33580

12

Analog Integrated Circuit Device Data

Freescale Semiconductor

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