MPC5534MVZ80 데이터 시트보기 (PDF) - Freescale Semiconductor

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MPC5534MVZ80

Microcontroller

Freescale Semiconductor 

Electrical Characteristics

Table 13. eQADC Conversion Specifications (Operating) (continued)

Num

Characteristic

Symbol

Min

Max

Unit

4 Resolution3

5 INL: 6 MHz ADC Clock

—

1.25

INL6

–4

—

mV

4

Counts3

6 INL: 12 MHz ADC Clock

INL12

–8

8

Counts

7 DNL: 6 MHz ADC Clock

DNL6

–3 4

34

Counts

8 DNL: 12 MHz ADC Clock

DNL12

–6 4

64

Counts

9 Offset Error with Calibration

OFFWC

–4 5

45

Counts

10 Full Scale Gain Error with Calibration

GAINWC

–8 6

86

Counts

11 Disruptive Input Injection Current 7, 8, 9, 10

IINJ

–1

1

mA

12 Incremental Error due to injection current. All channels have EINJ

–4

same 10kΩ < Rs <100kΩ

Channel under test has Rs=10kΩ,

IINJ=IINJMAX,IINJMIN

4

Counts

13 Total Unadjusted Error for single ended conversions with

TUE

–4

calibration11, 12, 13, 14, 15

4

Counts

1 Conversion characteristics vary with FADCLK rate. Reduced conversion accuracy occurs at maximum FADCLK rate. The

maximum value is based on 800KS/s and the minimum value is based on 20MHz oscillator clock frequency divided by a

maximum 16 factor.

2 Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that

the ADC is ready to perform conversions.

3 At VRH – VRL = 5.12 V, one lsb = 1.25 mV = one count

4 Guaranteed 10-bit monotonicity

5 The absolute value of the offset error without calibration ≤ 100 counts.

6 The absolute value of the full scale gain error without calibration ≤ 120 counts.

7 Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater than

VRH and 0x000 for values less than VRL. This assumes that VRH ≤ VDDA and VRL ≥ VSSA due to the presence of the sample

amplifier. Other channels are not affected by non-disruptive conditions.

8 Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do

not affect device reliability or cause permanent damage.

9 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate

resistance values using VPOSCLAMP = VDDA + 0.5V and VNEGCLAMP = – 0.3 V, then use the larger of the calculated values.

10 Condition applies to two adjacent pads on the internal pad.

11 The TUE specification will always be better than the sum of the INL, DNL, offset, and gain errors due to canceling errors.

12 TUE does not apply to differential conversions.

13 Measured at 6 MHz ADC clock. TUE with a 12 MHz ADC clock is: –16 counts < TUE < 16 counts.

14 TUE includes all internal device error such as internal reference variation (75% Ref, 25% Ref)

15 Depending on the customer input impedance, the Analog Input Leakage current (DC Electrical specification 35a) may affect

the actual TUE measured on analog channels AN12, AN13, AN14, AN15.

MPC5534 Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

21

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