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TP83C251SQ16 데이터 시트보기 (PDF) - Intel

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TP83C251SQ16 Datasheet PDF : 36 Pages
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8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
5.1 D.C. Characteristics
Parameter values apply to all devices unless otherwise indicated.
Symbol
Table 9. DC Characteristics at VCC = 4.5 – 5.5 V
Parameter
Min
Typical
Max
Units Test Conditions
VIL
Input Low Voltage
-0.5
(except EA#)
0.2VCC – 0.1
V
VIL1
Input Low Voltage
0
(EA#)
0.2VCC – 0.3
V
VIH
Input High Voltage
0.2VCC + 0.9
(except XTAL1, RST)
VCC + 0.5
V
VIH1
Input High Voltage
(XTAL1, RST)
0.7VCC
VCC + 0.5
V
VOL
Output Low Voltage
(Port 1, 2, 3)
0.3
0.45
1.0
V
IOL = 100 µA
IOL = 1.6 mA
IOL = 3.5 mA
(Note 1, Note 2)
VOL1
Output Low Voltage
(Port 0, ALE, PSEN#)
0.3
0.45
1.0
V
IOL = 200 µA
IOL = 3.2 mA
IOL = 7.0 mA
(Note 1, Note 2)
VOH
Output High Voltage
VCC – 0.3
(Port 1, 2, 3, ALE,
PSEN#)
VCC – 0.7
VCC – 1.5
V
IOH = -10 µA
IOH = -30 µA
IOH = -60 µA
(Note 3)
NOTES:
1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
port 0
26 mA
ports 1–3
15 mA
Maximum Total IOL for
all output pins
71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed
to sink current greater than the listed test conditions.
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into
the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive
loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to
qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic.
3. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specifica-
tion when the address lines are stabilizing.
4. Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed.
16
PRELIMINARY

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