M80C186EB-8 데이터 시트보기 (PDF) - Intel

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M80C186EB-8

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR

Intel 

Name

VCC

VSS

CLKIN

OSCOUT

CLKOUT

RESIN

RESOUT

PDTMR

NMI

TEST BUSY

AD15 0

A18 16

A19 ONCE

M80C186EB

Type

I

A(E)

O

H(Q)

R(Q)

P(Q)

O

H(Q)

R(Q)

P(Q)

I

A(L)

O

H(0)

R(1)

P(0)

IO

A(L)

H(WH)

R(Z)

P(1)

I

A(E)

I

A(E)

IO

S(L)

H(Z)

R(Z)

P(X)

H(Z)

R(WH)

P(X)

Table 4 M80C186EB Pin Descriptions

Description

POWER connections consist of four pins which must be shorted

externally to a VCC board plane

GROUND connections consist of six pins which must be shorted

externally to a VSS board plane

CLocK INput is an input for an external clock An external oscillator

operating at two times the required M80C186EB operating frequency

can be connected to CLKIN For crystal operation CLKIN (along with

OSCOUT) are the crystal connections to an internal Pierce oscillator

OSCillator OUTput is only used when using a crystal to generate the

external clock OSCOUT (along with CLKIN) are the crystal

connections to an internal Pierce oscillator This pin is not to be used

as 2X clock output for non-crystal applications (i e this pin is N C for

non-crystal applications) OSCOUT does not float in ONCE mode

CLocK OUTput provides a timing reference for inputs and outputs of

the processor and is one-half the input clock (CLKIN) frequency

CLKOUT has a 50% duty cycle and transistions every falling edge of

CLKIN

RESet IN causes the M80C186EB to immediately terminate any bus

cycle in progress and assume an initialized state All pins will be

driven to a known state and RESOUT will also be driven active The

rising edge (low-to-high) transition synchronizes CLKOUT with CLKIN

before the M80C186EB begins fetching opcodes at memory location

0FFFF0H

RESet OUTput that indicates the M80C186EB is currently in the

reset state RESOUT will remain active as long as RESIN remains

active

Power-Down TiMeR pin (normally connected to an external

capacitor) that determines the amount of time the M80C186EB waits

after an exit from power down before resuming normal operation The

duration of time required will depend on the startup characteristics of

the crystal oscillator

Non-Maskable Interrupt input causes a TYPE-2 interrupt to be

serviced by the CPU NMI is latched internally

TEST is used during the execution of the WAIT instruction to

suspend CPU operation until the pin is sampled active (LOW) TEST

is alternately known as BUSY when interfacing with an M80C187

numerics coprocessor

These pins provide a multiplexed Address and Data bus During the

address phase of the bus cycle address bits 0 through 15 are

presented on the bus and can be latched using ALE 8- or 16-bit data

information is transferred during the data phase of the bus cycle

These pins provide multiplexed Address during the address phase of

the bus cycle Address bits 16 through 19 are presented on these

pins and can be latched using ALE These pins are driven to a logic 0

during the data phase of the bus cycle During a processor reset

(RESIN active) A19 ONCE is used to enable ONCE mode A18 16

must not be driven low during reset or improper M80C186EB

operation may result

15

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