M80C186EB-8 데이터 시트보기 (PDF) - Intel
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M80C186EB-8 Datasheet PDF : 56 Pages
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M80C186EB
AC SPECIFICATIONS
AC Characteristics M80C186EB-13
Symbol
Parameter
INPUT CLOCK
TF
CLKIN Frequency
TC
CLKIN Period
TCH
CLKIN High Time
TCL
CLKIN Low Time
TCR
CLKIN Rise Time
TCF
CLKIN Fall Time
OUTPUT CLOCK
TCD
CLKIN to CLKOUT Delay
T
CLKOUT Period
TPH
CLKOUT High Time
TPL
CLKOUT Low Time
TPR
CLKOUT Rise Time
TPF
CLKOUT Fall Time
OUTPUT DELAYS
TCHOV1
ALE S2 0 DEN DT R BHE
LOCK A19 16
TCHOV2
TCLOV1
GCS0 7 LCS UCS NCS RD WR
BHE DEN LOCK RESOUT HLDA
T0OUT T1OUT A19 16
TCLOV2
RD WR GCS7 0 LCS UCS
AD15 0 NCS INTA1 0 S2 0
TCHOF
RD WR BHE DT R
LOCK S2 0 A19 16
TCLOF
DEN AD15 0
SYNCHRONOUS INPUTS
TCHIS
TEST NMI INT4 0 BCLK1 0
T1 0IN READY CTS1 0 P2 6 P2 7
TCHIH
TEST NMI INT4 0 BCLK1 0
T1 0IN READY CTS1 0
TCLIS
TCLIH
TCLIS
TCLIH
AD15 0 READY
READY AD15 0
HOLD PEREQ ERROR
HOLD PEREQ ERROR
Min
0
38 34
12
12
1
1
0
(T 2) b 5
(T 2) b 5
1
1
1
1
0
0
10
3
10
3
10
3
Max
26 08
%
%
%
8
8
23
2 TC
(T 2) a 5
(T 2) a 5
6
6
25
30
25
30
25
25
NOTES
1 See AC Timing Waveforms for waveforms and definition
2 Measure at VIH for high time VIL for low time
3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL
4 Specified for a 50 pF load see Figure 16 for capacitive derating information
5 Specified for a 50 pF load see Figure 17 for rise and fall times outside 50 pF
6 See Figure 17 for rise and fall times
7 TCHOV1 applies to BHE LOCK and A19 16 only after a HOLD release
8 TCHOV2 applies to RD and WR only after a HOLD release
9 Setup and Hold are required to guarantee recognition
10 Setup and Hold are required for proper M80C186EB operation
11 Not tested
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
12
12
13
13
14
1
1
1
15
15
1467
1468
146
146
1 11
1 11
19
19
1 10
1 10
19
19
25
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