VQ87C196KC 데이터 시트보기 (PDF) - Intel

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VQ87C196KC

16-BIT HIGH-PERFORMANCE CHMOS MICROCONTROLLERS WITH ON-CHIP EPROM

Intel 

M87C196KC M87C196KD

M87C196KC DESIGN INFORMATION

M87C196KC Enhanced Feature Set over the M80C196KB

1 The M87C196KC has twice the RAM of the M80C196KB and 16 Kbytes of EPROM Also a Vertical

Register Windowing Scheme allows the extra 256 bytes of RAM to be used as registers This greatly

reduces the context switching time

2 Peripheral Transaction Server (PTS) The PTS is an alternative way to service an interrupt reducing latency

and overhead Each interrupt can be mapped to its PTS channel which acts like a DMA channel Each

interrupt can now do a single or block transfer without executing an interupt service routine Special PTS

modes exist for the A D converter HSI and HSO

3 Two extra Pluse Width Modulated outputs The M87C196KC has added 2 PWM outputs that are functional-

ly compatible to the 80C196KB PWM

4 Timer2 Internal Clocking Timer2 can now be clocked with an internal source every 1 or 8 state times

5 The A D can now perform an 8- as well as a 10-bit conversion This trades off resolution for a faster

conversion time

6 Additional On-chip Memory Security Two UPROM (Uneraseable Programmable Read Only Memory) bits

can be programmed to disable the bus controller for external code and data fetches Once programmed a

UPROM bit cannot be erased By shutting off the bus controller for external fetches no one can try and

gain access to your code by executing from external memory

7 New Instructions The M87C196KC has 5 new instructions An exchange (XCHB XCHW) instruction swaps

two memory locations an Interruptable Block Move Instruction (BMOVI) a Table Indirect Jump (TIJMP)

instruction and two instructions for enabling and disabling the PTS (EPTS DPTS)

M80C196KB TO M87C196KC DESIGN

CONSIDERATIONS

1 Memory Map The M87C196KC has 512 bytes of

RAM SFRs and 16K of EPROM The extra 256

bytes of RAM will reside in locations 100H–1FFH

and the extra 8K of EPROM will reside in loca-

tions 4000H–5FFFH These locations are exter-

nal memory on the M80C196KB

2 EPROM programming The M87C196KC has a

different programming algorithm to support 16K

of on-board memory

3 ONCE Mode Entry The ONCE mode is entered

on the M87C196KC by driving the TXD pin low on

the rising edge of RESET The TXD pin is held

high by a pullup that is specified at 1 4 mA and

remain at 2 0V This Pullup must not be overrid-

den or the M87C196KC will enter the ONCE

mode

4 During the bus HOLD state the M87C196KC

weakly holds RD WR ALE BHE and INST in

their inactive states The 80C196KB only holds

ALE in its inactive state

5 A RESET pulse from the M87C196KC is 16

states rather than 4 states as on the 80C196KB

(i e a watchdog timer overflow) This provides a

longer RESET pulse for other devices in the sys-

tem

6 The CDE pin on the KB has become a VSS pin on

the KC to support 16 MHz operation

M87C196KC ERRATA

1 Missed EXTINT on P0 7

The 80C196KC20 could possibly miss an

EXTINT on P0 7 See faxback 2049

2 HIS MODE divide-by-eight

See Faxback 2192

3 IPD hump

See Faxback 2311

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