S3C44B0X 데이터 시트보기 (PDF) - Samsung

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S3C44B0X

RISC MICROPROCESSOR

Samsung 

PRODUCT OVERVIEW

S3C44B0X RISC MICROPROCESSOR

Table 1-2. 160-Pin FBGA Pin Assignment (Continued)

Pin No.

L1

L2

L3

L4

L5

L6

L7

L8

L9

L10

L11

L12

L13

L14

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

M13

M14

Pin Name

VDD

VSS

ExINT2/nCTS0/GPG2

TDO

nRESET

OM3

SIORDY/TxD1/IISDO/GPF6

EXTAL0

TOUT1/TCLK/GPE4

VSSIO

VDDADC

VDDRTC

XTAL1

EXTAL1

ExINT4/IISCLK/GPG4

ExINT3/nRTS0/GPG3

TDI

CLKout/GPE0

OM2

SIORxD/RxD1/IISDI/GPF7

IICSCL/GPF0

VDD

TOUT0/GPE3

TOUT4/VD7/GPE7

AIN1

AVCOM

AREFB

AREFT

Pin No.

N1

N2

N3

N4

N5

N6

N7

N8

N9

N10

N11

N12

N13

N14

P1

P2

P3

P4

P5

P6

P7

P8

P9

P10

P11

P12

P13

P14

Pin Name

ExINT5/IISDI/GPG5

ExINT7/IISLRCK/GPG7

TMS

VDDIO

OM0

ENDIAN/CODECLK/GPE8

SIOTxD/nRTS1/IISLRCK/GPF5

XTAL0

EXTCLK

TOUT3/VD6/GPE6

AIN0

AIN2

AIN6

AIN7

ExINT6/IISDO/GPG6

nTRST

TCK

VSSIO

OM1

SIOCLK/nCTS1/IISCLK/GPF8

IICSDA/GPF1

VSS

PLLCAP

TOUT2/TCLK/GPE5

VSSADC

AIN3

AIN4

AIN5

NOTES :

1. OM[3:0] and ENDIAN value are latched only at the rising edge of nRESET. Therefore, when nRESET is L, the pins of

OM[3:0] and ENDIAN are in input state. After nRESET becomes H, the pin of ENDIAN will be in output state.

2. The @BUS REQ. shows the pin states at the external bus, which is used by the other bus master. The @STOP shows

the pin states when S3C44B0X is in STOP mode.

3. ' − ' mark indicates the unchanged pin state at STOP mode or Bus released mode.

4. IICSDA,IICSCL pins are open-drain type.

5. AI/AO means analog input/output.

1-16

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