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SST32HF202

Multi-Purpose Flash (MPF) + SRAM ComboMemory

Silicon Storage Technology 

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

operation consists of three steps. The first step is the three-

byte load sequence for Software Data Protection. The sec-

ond step is to load word address and word data. During the

Word-Program operation, the addresses are latched on the

falling edge of either BEF# or WE#, whichever occurs last.

The data is latched on the rising edge of either BEF# or

WE#, whichever occurs first. The third step is the internal

Program operation which is initiated after the rising edge of

the fourth WE# or BEF#, whichever occurs first. The Pro-

gram operation, once initiated, will be completed, within 20

µs. See Figures 6 and 7 for WE# and BEF# controlled Pro-

gram operation timing diagrams and Figure 17 for flow-

charts. During the Program operation, the only valid flash

Read operations are Data# Polling and Toggle Bit. During

the internal Program operation, the host is free to perform

additional tasks. Any SDP commands loaded during the

internal Program operation will be ignored.

Flash Sector/Block-Erase Operation

The Flash Sector/Block-Erase operation allows the system

to erase the device on a sector-by-sector (or block-by-

block) basis. The SST32HF20x/40x offer both Sector-

Erase and Block-Erase mode. The sector architecture is

based on uniform sector size of 2 KWord. The Block-Erase

mode is based on uniform block size of 32 KWord. The

Sector-Erase operation is initiated by executing a six-byte

command sequence with Sector-Erase command (30H)

and sector address (SA) in the last bus cycle. The address

lines A16-A11, for SST32HF201/202, and A17-A11, for

SST32HF401/402, are used to determine the sector

address. The Block-Erase operation is initiated by execut-

ing a six-byte command sequence with Block-Erase com-

mand (50H) and block address (BA) in the last bus cycle.

The address lines A16-A15, for SST32HF201/202, and A17-

A15, for SST32HF401/402, are used to determine the block

address. The sector or block address is latched on the fall-

ing edge of the sixth WE# pulse, while the command (30H

or 50H) is latched on the rising edge of the sixth WE#

pulse. The internal Erase operation begins after the sixth

WE# pulse. The End-of-Erase operation can be deter-

mined using either Data# Polling or Toggle Bit methods.

See Figures 11 and 12 for timing waveforms. Any com-

mands issued during the Sector- or Block-Erase operation

are ignored.

Flash Chip-Erase Operation

The SST32HF20x/40x provide a Chip-Erase operation,

which allows the user to erase the entire memory array to

the “1” state. This is useful when the entire device must be

quickly erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command (10H)

at address 5555H in the last byte sequence. The Erase

operation begins with the rising edge of the sixth WE# or

CE#, whichever occurs first. During the Erase operation,

the only valid read is Toggle Bit or Data# Polling. See Table

4 for the command sequence, Figure 9 for timing diagram,

and Figure 20 for the flowchart. Any commands issued dur-

ing the Chip-Erase operation are ignored.

Write Operation Status Detection

The SST32HF20x/40x provide two software means to

detect the completion of a Write (Program or Erase) cycle,

in order to optimize the system Write cycle time. The soft-

ware detection includes two status bits: Data# Polling

(DQ7) and Toggle Bit (DQ6). The End-of-Write detection

mode is enabled after the rising edge of WE#, which ini-

tiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the Write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data may appear to con-

flict with either DQ7 or DQ6. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is valid.

Flash Data# Polling (DQ7)

When the SST32HF20x/40x flash memory banks are in

the internal Program operation, any attempt to read DQ7

will produce the complement of the true data. Once the

Program operation is completed, DQ7 will produce true

data. Note that even though DQ7 may have valid data

immediately following the completion of an internal Write

operation, the remaining data outputs may still be invalid:

valid data on the entire data bus will appear in subsequent

successive Read cycles, after an interval of 1 µs. During

internal Erase operation, any attempt to read DQ7 will pro-

duce a ‘0’. Once the internal Erase operation is completed,

DQ7 will produce a ‘1’. The Data# Polling is valid after the

rising edge of the fourth WE# (or BEF#) pulse for Program

operation. For Sector- or Block-Erase, the Data# Polling is

valid after the rising edge of the sixth WE# (or BEF#) pulse.

See Figure 8 for Data# Polling timing diagram and Figure

18 for a flowchart.

©2001 Silicon Storage Technology, Inc.

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