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SST32HF202

Multi-Purpose Flash (MPF) + SRAM ComboMemory

Silicon Storage Technology 

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

Flash Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating ‘1’s

and ‘0’s, i.e., toggling between 1 and 0. When the internal

Program or Erase operation is completed, the toggling will

stop. The flash memory bank is then ready for the next

operation. The Toggle Bit is valid after the rising edge of the

fourth WE# (or BEF#) pulse for Program operation. For

Sector- or Bank-Erase, the Toggle Bit is valid after the rising

edge of the sixth WE# (or BEF#) pulse. See Figure 9 for

Toggle Bit timing diagram and Figure 18 for a flowchart.

Flash Memory Data Protection

The SST32HF20x/40x flash memory bank provides both

hardware and software features to protect nonvolatile data

from inadvertent writes.

Flash Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less than

5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#

high will inhibit the Flash Write operation. This prevents

inadvertent writes during power-up or power-down.

CONCURRENT READ/WRITE STATE TABLE

Flash

Program/Erase

Program/Erase

SRAM

Read

Write

The device will ignore all SDP commands when an Erase

or Program operation is in progress. Note that Product

Identification commands use SDP; therefore, these com-

mands will also be ignored while an Erase or Program

operation is in progress.

Product Identification

The Product Identification mode identifies the devices as

the SST32HF20x/40x and manufacturer as SST. This

mode may be accessed by software operations only.

The hardware device ID Read operation, which is typi-

cally used by programmers, cannot be used on this

device because of the shared lines between flash and

SRAM in the multi-chip package. Therefore, applica-

tion of high voltage to pin A9 may damage this device.

Users may use the software Product Identification opera-

tion to identify the part (i.e., using the device ID) when using

multiple manufacturers in the same socket. For details, see

Tables 3 and 4 for software operation, Figure 13 for the

software ID entry and Read timing diagram, and Figure 19

for the ID entry command sequence flowchart.

Flash Software Data Protection (SDP)

The SST32HF20x/40x provide the JEDEC approved soft-

ware data protection scheme for all flash memory bank

data alteration operations, i.e., Program and Erase. Any

Program operation requires the inclusion of a series of

three-byte sequence. The three-byte load sequence is

used to initiate the Program operation, providing optimal

protection from inadvertent Write operations, e.g., during

the system power-up or power-down. Any Erase operation

requires the inclusion of six-byte load sequence. The

SST32HF20x/40x devices are shipped with the software

data protection permanently enabled. See Table 4 for the

specific software command codes. During SDP command

sequence, invalid SDP commands will abort the device to

the read mode, within Read Cycle Time (TRC).

Concurrent Read and Write Operations

The SST32HF20x/40x provide the unique benefit of being

able to read from or write to SRAM, while simultaneously

erasing or programming the Flash. This allows data alter-

ation code to be executed from SRAM, while altering the

data in Flash. The following table lists all valid states.

TABLE 1: PRODUCT IDENTIFICATION

Manufacturer’s ID

Device ID

SST32HF201/202

SST32HF401/402

Address

0000H

0001H

0001H

Data

00BFH

2789H

2780H

T1.0 557

Product Identification Mode Exit/Reset

In order to return to the standard read mode, the Software

Product Identification mode must be exited. Exiting is

accomplished by issuing the Exit ID command sequence,

which returns the device to the Read operation. Please

note that the software-reset command is ignored during an

internal Program or Erase operation. See Table 4 for soft-

ware command codes, Figure 14 for timing waveform and

Figure 19 for a flowchart.

Design Considerations

SST recommends a high frequency 0.1 µF ceramic capac-

itor to be placed as close as possible between VDD and

VSS, e.g., less than 1 cm away from the VDD pin of the

©2001 Silicon Storage Technology, Inc.

4

S71209-00-000 9/01 557

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