28F016XS 데이터 시트보기 (PDF) - Intel

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28F016XS

16-MBIT (1 MBIT x 16, 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY

Intel 

E

28F016XS FLASH MEMORY

2.1 Lead Descriptions (Continued)

Symbol

CLK

ADV#

RY/BY#

WP#

BYTE#

3/5#

VPP

VCC

Type

Name and Function

INPUT

CLOCK: Provides the fundamental timing and internal operating frequency.

CLK latches input addresses in conjunction with ADV#, times out the desired

output SFI Configuration as a function of the CLK period, and synchronizes

device outputs. CLK can be slowed or stopped with no loss of data or

synchronization. CLK is ignored during program operations.

INPUT

OPEN

DRAIN

OUTPUT

INPUT

ADDRESS VALID: Indicates that a valid address is present on the address

inputs. ADV# low at the rising edge of CLK latches the address on the address

inputs into the flash memory and initiates a read access to the even or odd

bank depending on the state of A1. ADV# is ignored during program operations.

READY/BUSY: Indicates status of the internal WSM. When low, it indicates

that the WSM is busy performing an operation. RY/BY# high indicates that the

WSM is ready for new operations, erase is suspended, or the device is in deep

power-down mode. This output is always active (i.e., not floated to tri-state off

when OE# or CE0#, CE1# are high).

WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile lock-bit

for each block. When WP# is low, those locked blocks as reflected by the

Block-Lock Status bits (BSR.6), are protected from inadvertent data programs

or erases. When WP# is high, all blocks can be written or erased regardless of

the state of the lock-bits. The WP# input buffer is disabled when RP#

transitions low (deep power-down mode).

INPUT

BYTE ENABLE: BYTE# low places device in x8 mode. All data is then input or

output on DQ0–7, and DQ8–15 float. Address A0 selects between the high and

low byte. BYTE# high places the device in x16 mode, and turns off the A0 input

buffer. Address A1 then becomes the lowest order address.

INPUT

3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V

operation. 3/5# low configures internal circuits for 5.0V operation.

NOTE:

Reading the array with 3/5# high in a 5.0V system could damage the device.

Reference the power-up and reset timings (Section 5.10) for 3/5# switching

delay to valid data.

SUPPLY

PROGRAM/ERASE POWER SUPPLY (12.0V ± 0.6V, 5.0V ± 0.5V) :

For erasing memory array blocks or writing words/bytes into the flash array.

VPP = 5.0V ± 0.5V eliminates the need for a 12.0V converter, while the 12.0V ±

0.6V option maximizes program/erase performance.

Successful completion of program and erase attempts is inhibited with VPP at

or below 1.5V. Program and erase attempts with VPP between 1.5V and 4.5V,

between 5.5V and 11.4V, and above 12.6V produce spurious results and

should not be attempted.

SUPPLY

DEVICE POWER SUPPLY (3.3V ± 5%, 5.0V ± 5%):

To switch 3.3V to 5.0V (or vice versa), first ramp VCC down to GND, and then

power to the new VCC voltage. Do not leave any power pins floating.

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