STA120 데이터 시트보기 (PDF) - STMicroelectronics

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STA120

DIGITAL AUDIO INTERFACE RECEIVER

STMicroelectronics 

STA120

PINS DESCRIPTION (continued)

N.

Name

Description

16

SEL Select.Control pin that selects either channel status information (SEL = 1) or error and frequency

information (SEL = 0) to be displayed on six (C0, Ca Cb, Cc, Cd, Ce) pins.

27

Ce Channel Status Output Bits.These pin are dual Function with the "C" bits selected when SEL is

high. Channel status information is displayed for the channel selected by CS12. C0, which is

channel status bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further

controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.

F2 Frequency reporting Bits.Encoded sample frequency information that is enabled by bringing SEL

low. A proper clock on FCK must be input for at least two thirds of a channel status block for

these pins to be valid. They are updated three times per block, starting at the block boundary.

28

VERF Validity + Error Flag. A logical OR'ing of the validity bit from the received data and the error flag.

May be used by interpolation filters to interpolate through errors.

Receiver Interface

9

RXP Line Receiver. (RS422 compatible)

10

RXN Line Receiver. (RS422 compatible)

Phase Locked Loop

19

MCK Master Clock.Low Jitter clock output of 256 times the received sample frequency.

20

FILT Filter.An external 330 Ohm resistor and 0.47µF capacitor in parallel with a 15nF capacitor is

required from FILT pin to analog ground.

25

ERF Error Flag,Signals that an error has occurred while receiving the audio sample currently being

read from the serial port. Three errors cause ERF to go high: a parity or biphase coding violation

during the current sample, or an out of lock PLL receiver.

DIGITAL CHARACTERISTICS (Tamb = 25°C; VD+, VA+ = 3.3V ±10%)

Symbol

Parameter

Test Condition

VD+,VA+ Power supply voltage Range

VIH High-Level Input Voltage

VIL Low-Level Input Voltage

VOH High-Level Output Voltage

IO = 200µA

VOL Low-Level Output Voltage

IO = 3.2mA

Iin Input Leakage Current

FS Input Sample Frequency

(Note 1)

MCK Master Clock frequency

(Note 1)

tj

MCK Clock Jitter

MCK Duty Cycle

(high time/cycle time)

Idd_ST Static Idd (MCK = 0)

Idd_DYN Dynamic Idd

Note 1: FS is defined as the incoming audio sample frequency per channel.

Min.

3.0

2.0

Typ.

3.3

VDD-1.0

1.0

25

6.4 256xFS

300

50

0.1

6

Max.

3.6

+0.8

0.4

10

96

25

1

15

Unit

V

V

V

V

V

µA

kHz

MHz

ps RMS

%

mA

mA

SWITCHING CHARACTERISTICS - SERIAL PORTS (Tamb = 25°C; VD+, VA+ = 3.3V ±10%)

Symbol

Parameter

Test Condition

Min.

Typ.

Max. Unit

fsck SCK Frequency

(Note 2)

OWRx32

Hz

Note 2: The output word rate, OWR, refers to the frequency at which an audio sample is output from the part. (A stereo pair is two audio

samples). Therefore, in Master mode, there are always 32 SCK periods in one audio sample. In Slave mode 32 SCK periods must

be provided in most serial port formats.

4/15

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