STK11C68 데이터 시트보기 (PDF) - Unspecified
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STK11C68 Datasheet PDF : 10 Pages
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STK11C68
SRAM WRITE CYCLES #1 & #2
(VCC = 5.0V + 10%)b
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
STK11C68-20
MIN MAX
STK11C68-25 STK11C68-35 STK11C68-45
UNITS
MIN MAX MIN MAX MIN MAX
12
tAVAV
tAVAV
tWC Write Cycle Time
20
13 tWLWH
tWLEH
tWP Write Pulse Width
15
14 tELWH
tELEH
tCW Chip Enable to End of Write
15
15 tDVWH
tDVEH
tDW Data Set-up to End of Write
8
16 tWHDX
tEHDX
tDH Data Hold after End of Write
0
17 tAVWH
tAVEH
tAW Address Set-up to End of Write
15
18 tAVWL
tAVEL
tAS Address Set-up to Start of Write
0
19 tWHAX
tEHAX
tWR Address Hold after End of Write
0
20 tWLQZi, j
tWZ Write Enable to Output Disable
7
21 tWHQX
tOW Output Active after End of Write
5
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledk
25
35
45
ns
20
25
30
ns
20
25
30
ns
10
12
15
ns
0
0
0
ns
20
25
30
ns
0
0
0
ns
0
0
0
ns
10
13
15
ns
5
5
5
ns
ADDRESS
E
12
tAVAV
14
tELWH
19
tWHAX
W
DATA IN
DATA OUT
18
tAVWL
17
tAVWH
13
tWLWH
20
tWLQZ
PREVIOUS DATA
15
tDVWH
DATA VALID
HIGH IMPEDANCE
SRAM WRITE CYCLE #2: E Controlledk
ADDRESS
E
18
tAVEL
12
tAVAV
14
tELEH
16
tWHDX
21
tWHQX
19
tEHAX
W
DATA IN
DATA OUT
17
tAVEH
13
tWLEH
15
tDVEH
DATA VALID
HIGH IMPEDANCE
16
tEHDX
June 1999
4-24
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