CS5512-BS(2000) 데이터 시트보기 (PDF) - Cirrus Logic

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CS5512-BS
(Rev.:2000)

16 and 20-Bit, 8-Pin ∆Σ ADC

Cirrus Logic 

and the consumed sleep power will be greater. To

exit sleep and return to normal mode, the user must

return SCLK low for at least 10 µs. After a sleep is

exited, the ADCs reset all their internal logic, in-

cluding their digital filters, and begin performing

conversions. Since the filters are reset, the first

three conversion after returning to normal mode

will not be fully settled.

2.8 PCB Layout

The CS5510/11/12/13 should be placed entirely

over the analog ground. Place the analog-digital

plane split immediately adjacent to the digital pins

of the chip. See the CDB5510/11/12/13 data sheet

and Applications Note 18 for more detailed layout

guidelines. Also note that applications engineering

provides a Free and Confidential Schematic Re-

view Service.

CS5510/11/12/13

DS337F1

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