AT91M40400 데이터 시트보기 (PDF) - Atmel Corporation
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AT91M40400 Datasheet PDF : 116 Pages
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Data Bus Width
A data bus width of 8 or 16 bits can be selected for each
chip select. This option is controlled by the DBW field in the
EBI_CSR (Chip Select Register) for the corresponding chip
select.
Figure 8 shows how to connect a 512K x 8-bit memory on
NCS2.
Figure 8. Memory Connection for an 8-Bit Data Bus
D0 - D7
D8 - D15
A1 - A18
EBI
A0
NWR1
NWR0
NRD
NCS2
D0 - D7
A1 - A18
A0
Write Enable
Output Enable
Memory Enable
Figure 9 shows how to connect a 512K x 16-bit memory on
NCS2.
Figure 9. Memory Connection for a 16-Bit Data Bus
Byte Write or Byte Select Access
Each chip select with a 16-bit data bus can operate with
one of two different types of write access:
• Byte Write Access supports two byte write and a single
read signal.
• Byte Select Access selects upper and/or lower byte with
two byte select lines, and separate read and write
signals.
This option is controlled by the BAT field in the EBI_CSR
(Chip Select Register) for the corresponding chip select.
Byte Write Access is used to connect 2 x 8-bit devices as a
16-bit memory page.
• The signal A0/NLB is not used.
• The signal NWR1/NUB is used as NWR1 and enables
upper byte writes.
• The signal NWR0/NWE is used as NWR0 and enables
lower byte writes.
• The signal NRD/NOE is used as NRD and enables half-
word and byte reads.
Figure 10 shows how to connect two 512K x 8-bit devices
in parallel on NCS2.
Figure 10. Memory Connection for 2 x 8-Bit Data Busses
D0 - D7
D8 - D15
A1 - A19
EBI
NLB
NUB
NWE
NOE
NCS2
D0 - D7
D8 - D15
A0 - A18
Low Byte Enable
High Byte Enable
Write Enable
Output Enable
Memory Enable
D0 - D7
D8 - D15
A1 - A19
EBI
A0
NWR1
NWR0
NRD
NCS2
D0 - D7
A0 - A18
Write Enable
Read Enable
Memory Enable
12
AT91M40400
D8 - D15
A0 - A18
Write Enable
Read Enable
Memory Enable
Byte Select Access is used to connect 16-bit devices in a
memory page.
• The signal A0/NLB is used as NLB and enables the
lower byte for both read and write operations.
• The signal NWR1/NUB is used as NUB and enables the
upper byte for both read and write operations.
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