UPD16661A 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD16661A

160-OUTPUT LCD COLUMN (SEGMENT) DRIVER WITH RAM

NEC => Renesas Technology 

µPD16661A

9. LIQUID-CRYSTAL TIMING GENERATION

9.1 Reset state

In the reset state, the internal counter is zero-cleared.

After the reset is released, the display OFF function operates during the 4-frame cycle, even if the /DOFF pin is

at H.

/RESET

/FRM

/DOUT

Internal state

1

2

3

4

5

6

Display OFF

Display ON

9.2 Liquid-crystal timing generation circuit

When the master mode is set with MS = H, this circuit generates the signals /FRM and STB at a duty ratio timing

of 1/240. It also generates L1 and L2, which are the drive voltage selection signals for the row driver.

The /FRM signal is generated twice per frame. The STB signal is generated 121 times per half frame, or 242

times per frame.

Generation of /FRM & STB signals

OSC1

/FRM

STB

121 1

2

121 1

2

Frame

121 1

2

Generation of L1 and L2 signals

STB

1 2 3 4 ⋅⋅⋅

L1

1 1 1 1 ⋅⋅⋅

L2

1 0 1 0 ⋅⋅⋅

1 2 3 4 ⋅⋅⋅

1 1 1 1 ⋅⋅⋅

0 1 0 1 ⋅⋅⋅

1 2 3 4 ⋅⋅⋅

0 0 0 0 ⋅⋅⋅

0 1 0 1 ⋅⋅⋅

1 2 3 4 ⋅⋅⋅

0 0 0 0 ⋅⋅⋅

1 0 1 0 ⋅⋅⋅

17

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