Table 17. BIT_CLK Timing
Symbol
Parameter
TCLK_PERIOD
TCLK_HIGH
TCLK_LOW
TCLK_DC
BIT_CLK Frequency
BIT_CLK Period
BIT_CLK Output Jitter
BIT_CLK Pulse Width (high)
BIT_CLK Pulse Width (low)
BIT_CLK Duty Cycle
VT1616 6-Channel AC97 Codec with S/PDIF
Min
32.56
32.56
40
Typ
12.288
81.4
40.7
40.7
Max
750
48.84
48.84
60
Unit
MHz
ns
ps
ns
ns
%
BIT_CLK
TCLK_HIGH
TCLK_LOW
TCLK_PERIOD
Figure 9. BIT_CLK Timing
Table 18. SYNC Timing
Symbol
Parameter
SYNC Frequency
TSYNC_PERIOD SYNC Period
TSYNC_HIGH SYNC Pulse Width (high)
TSYNC_LOW SYNC Pulse Width (low)
Min
Typ
Max
Unit
48
KHz
20.8
µs
1.3
µs
19.5
µs
SYNC
TSYNC_HIGH = 16 TCLK_PERIOD
TSYNC_LOW= 240 TCLK_PERIOD
TSYNC_PERIOD
Figure 10. SYNC Timing
Revision 1.5, October 11, 2002
36
Data Sheet