WM8816 데이터 시트보기 (PDF) - Wolfson Microelectronics plc
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WM8816 Datasheet PDF : 13 Pages
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ELECTRICAL CHARACTERISTICS
TEST CONDITIONS
AVDD=5.0V, AGND = 0V, TA = 25°C, unless otherwise stated.
PARAMETER
SYMBOL TEST CONDITIONS
MIN
Analogue Inputs / Outputs
Input resistance
RIN
For any gain
7
Input capacitance
CIN
For any gain
Op-amp gain = -15.5
Input offset voltage (note 1)
Voffset
Op-amp gain = 1
Op-amp gain = 15.5
Supply current
IDD
From AVDD / AGND
Power supply rejection ratio
(Note 2)
PSRR
From AVDD
Gain Control
Gain range
G
-111.5
Gain step size
D
Gain error (Note 2)
DE
Lowest gains
guaranteed by
design, not tested in
production.
Gain match error (Note 2)
ME
Between channels
Mute attenuation
MATT
113
Audio Performance
Noise (Note 2)
Gain = 0dB
VIN = 0V, VOUT with OP275,
A-weighed
N
Gain = -60dB
Gain = mute
Total Harmonic Distortion plus
Noise
THD+N
VIN= 1Vrms, gain=0dB,
VOUT with OP275,
DC to 20 kHz
Dynamic Range (Note 2)
DNR
120
Crosstalk (Note 2)
CR
Between channels,
-100
gain=0dB, fIN=1kHz
Digital Inputs / Outputs
Input low voltage
Input high voltage
Output low voltage
Output high voltage
VIL
All digital inputs
VIH
All digital inputs 0.7 DVDD
VOL
ILoad = 2mA
VOH
ILoad = 2mA
DVDD -0.4
Control Interface Timing
Clock Frequency
Period of CCLK high
fCCLK
tWHC
VIH to VIH
500
Period of CCLK low
tWLC
VIL to VIL
500
Rise time of CCLK
tRC
VIL to VIH
Fall time of CCLK
tFC
VIH to VIL
Hold time, CCLK high to CSB low
tHCSH
20
Setup time, CSB low to CCLK
tSSLCH
100
high
Setup time, valid DATA to CCLK
tSDCH
100
high
Hold time, CCLK high to invalid
tHCHD
100
DATA
Setup time, CCLK low to valid
DATA
tDCLD
Load = 100pF
Hold time, CSB high or 16th
CCLK low to invalid DATA
tDSZ
Load = 3.3kΩ
20
w
TYP
10
2
0.8
3
12
2.5
80
0.5
4
2.5
0.001
(100)
130
-110
WM8816
MAX
5
+15.5
0.5
UNIT
kΩ
pF
mV
mV
mV
mA
dB
dB
dB
dB
0.2
dB
dB
13
µVrms
%
(dB)
dB
dB
0.3 DVDD
0.4
1
100
100
200
200
V
V
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PP Rev 1.5 October 2004
5
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