CYS25G0101DX-AEXC(2010) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CYS25G0101DX-AEXC Datasheet PDF : 18 Pages
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CYS25G0101DX
AC Specifications
Table 7. AC Specifications - Parallel Interface
Parameter
tTS
tTXCLKI
tTXCLKID
tTXCLKIR
tTXCLKIF
tTXDS
tTXDH
tTOS
tTXCLKO
tTXCLKOD
tTXCLKOR
tTXCLKOF
tRS
tRXCLK
tRXCLKD
tRXCLKR
tRXCLKF
tRXDS
tRXDH
tRXPD
Description
TXCLKI Frequency (must be frequency coherent to REFCLK)
TXCLKI Period
TXCLKI Duty Cycle
TXCLKi Rise Time
TXCLKi Fall Time
Write Data Setup toof TXCLKI
Write Data Hold fromof TXCLKI
TXCLKO Frequency
TXCLKO Period
TXCLKO Duty Cycle
TXCLKO Rise Time
TXCLKO Fall Time
RXCLK Frequency
RXCLK Period
RXCLK Duty Cycle
RXCLK Rise Time[6]
RXCLK Fall Time[6]
Recovered Data Setup with reference to of RXCLK
Recovered Data Hold with reference to of RXCLK
Valid Propagation Delay
Table 8. AC Specifications - REFCLK [7]
Parameter
tREF
tREFP
tREFD
tREFT
tREFR
tREFF
Description
REFCLK Input Frequency
REFCLK Period
REFCLK Duty Cycle
REFCLK Frequency Tolerance — (relative to received serial data)[8]
REFCLK Rise Time
REFCLK Fall Time
Table 9. AC Specifications–CML Serial Outputs
Parameter
tRISE
tFALL
Description
CML Output Rise Time (20–80%, 100 balanced load)
CML Output Fall Time (80–20%, 100 balanced load)
Table 10. Jitter Specifications
Parameter
tTJ-TXPLL
tTJ-RXPLL
Description
Total Output Jitter for TX PLL (p-p)[9]
Total Output Jitter for TX PLL (rms)[9, 11]
Total Output Jitter for RX CDR PLL (p-p)[9]
Total Output Jitter for RX CDR PLL (rms)[9, 11]
Min
154.5
6.38
40
0.3
0.3
1.5
0.5
154.5
6.38
43
0.3
0.3
154.5
6.38
43
0.3
0.3
2.2
2.2
–1.0
Max
156.5
6.47
60
1.5
1.5
156.5
6.47
57
1.5
1.5
156.5
6.47
57
1.5
1.5
1.0
Unit
MHz
ns
%
ns
ns
ns
ns
MHz
ns
%
ns
ns
MHz
ns
%
ns
ns
ns
ns
ns
Min
154.5
6.38
35
–100
0.3
0.3
Max
156.5
6.47
65
+100
1.5
1.5
Unit
MHz
ns
%
ppm
ns
ns
Min
Typ Max Unit
60
170 ps
60
170 ps
Min Typ[10] Max[10] Unit
0.03 0.04 UI
0.007 0.008 UI
0.035 0.05 UI
0.008 0.01 UI
Notes
6. RXCLk rise time and fall times are measured at the 20 to 80 percentile region of the rising and falling edge of the clock signal.
7. The 155.52 MHz Reference Clock Phase Noise Limits for the CYS25G0101DX are shown in Figure 8.
8. +20 ppm is required to meet the SONET output frequency specification.
9. The RMS and P-to-P jitter values are measured using a 12 KHz to 20 MHz SONET filter.
10. Typical values are measured at room temperature and the Max values are measured at 0° C.
11. This device passes the Bellcore specification from -10° C to 85° C.
Document Number: 38-02009 Rev. *M
Page 12 of 18
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